How long does the FPGA complete the initialization?

[Altera_Forum]

Hi dears: 

  I found below information inside Altera configuration handbook:  "By default, the internal oscillator is the clock source for initialization. If the internal oscillator is used, the Arria GX device provides itself with enough clock cycles for proper initialization. "    And my question is that what is the number of the "enough clock cycles"? For I have some applications which want to control the FPGA and CPU's time of powering up to work.

[Altera_Forum]

After POR time has expired (the value is specified in the device handbooks), the initialization time requirement is mainly for reading the serial or parallel configuration device. The frequency range is also specified (the internal or external clock in case of AS configuration), the configuration stream size depends on your design.

[Altera_Forum]

Thanks for ur information! 

 Another question, the FPGA how to know which word or byte is the last one when configuring thru AS mode? Is there any sign inside configuration stream? If so, can user recognize it?

[Altera_Forum]

Obviously, there is a length information. If I remember right, it's documented somewhere with the NIOS II stuff, it has been recently mentioned in a forum thread. But I didn't yet need the information.

[Altera_Forum]

Anyway, thanks for ur inf!