Cylone II FPGA Clock input

[Altera_Forum]

In my design ，the FPGA uses single-end clock input, the clock is 40MHz signal ,3.3 Vpp and 6.6Vpp , the Voltage is -1.55~+1.55V and -3.3~+3.3V, but the FPGA 

I/O Voltage :-0.8V~4.1V. My question : Is it right that using the 40MHz signal as the FPGA clock input??

[Altera_Forum]

I can't understand you. What is "3.3 Vpp and 6.6Vpp , the Voltage is -1.55~+1.55V and -3.3~+3.3V, but the FPGA". If you clock generator is 3.3v you can connect this clock to 3.3v powered bank fpga.

[Altera_Forum]

Your specification suggests an AC coupled clock source and possibly signal overshoot. The FPGA maximum ratings must be unconditionally kept to avoid device damage. Also the level and maximum rise-time specifications of the respective I/O standard should be considered to achieve reliable operation.  

 As said, a usual 3.3V clock oscillator can be directly connected to the FPGA clock input, for traces longer than 1", a source side termination resistor may be recommended. If you have a non-standard clock source, a level conversion is most likely necessary.  P.S.: You may experience difficulties to measure the actual clock waveform with an usual passive oscilloscope probe and particularly it's unsuitable standard ground connection.

[Altera_Forum]

--- Quote Start ---  I can't understand you. What is "3.3 Vpp and 6.6Vpp , the Voltage is -1.55~+1.55V and -3.3~+3.3V, but the FPGA". If you clock generator is 3.3v you can connect this clock to 3.3v powered bank fpga.  --- Quote End ---    The two clock signals are 40MHz,3.3Vpp and 40MHz,6.6Vpp ,but the Voltage is not from 0V~3.3V and 0V~6.6V, 3.3Vpp means -1.55~+1.55V and 6.6Vpp means  -3.3~+3.3V, I don't know the clock source is usefull for the EP2C70F896C8??

[Altera_Forum]

FvM： thank you! You understand my questions. I have a usual 3.3V clock oscillator connected to the FPGA clock input, and at the same time ,I have another external interface to supply a clock input ,the source is -3.3V~3.V 40MHz signal,+3.3V is not bigger than specification(+4.1V), -3.3V is less than -0.8V too much ,I don't know whether it will cause some problem？

[Altera_Forum]

--- Quote Start ---  I don't know whether it will cause some problem？  --- Quote End ---  It will. At best, the negative voltage is cut by device internal substrate diodes, but you shouldn't rely on it. The general tool for level conversion is a fast comparator. As I said, not only the signal level, but also the rise time is significant for clocks. Slow edges can bring up double clocking and always introduces higher jitter. The processing of clock signals isn't particularly a FPGA topic, you can't expect detailed suggestions in the Altera literature. You should rather consult datasheets and application notes of fast comparators, e.g. from ADI, TI, Maxim, Linear or National or general electronics text books.  If the clock has sufficient fast edges, a series resistor and schottky diode limiter (connected to GND and VCCIO, either 3.3 or 2.5V) can be a suitable solution.

[Altera_Forum]

You need an external driver between the interface and the FPGA so that you generate clock from the FPGA to driver an than to the interface.

[Altera_Forum]

You can limit this signal by TVS diodes. Or you can use signal transformer and en example 74HC schmitt trigger.