I'm trying to implement a flip flop and i don't want it to have a reset pin. I just want 2 inputs D and CK and two outputs Q and notQ my VHDL code is shown below.--- Quote Start --- library IEEE;use IEEE.STD_LOGIC_1164.all; -- D type flip flop Entity flipflop is port ( D, CK : in std_logic; Q, notQ: out std_logic ); end entity; architecture random of flipflop is signal f1,f2,f3,f4,f5: std_logic ; begin f1 <= D nand CK; f2 <= not D; f3 <= ck nand f2; f4 <= f1 nand f5; f5 <= f3 nand f5 ; NotQ <= f5 ; Q <= f4; end random; --- Quote End --- My simulation file is attached. Can someone tell me have i done everything correctly? Is my simulation file correct and is my code correct too? Simulation file is in the pdf attachment
If it seems correct, then good.But you would never describe a flip-flop like this in an FPGA for several resons: 1. An FPGA has no gates, so has to build the design from LUTs 2. Because it is all gates, it is going to be affected by PVT (process, voltage, temperature) in that timing will change depending on PVT. 3. There are dedicated flip-flops in the FPGA fabric. From the code it looks like you coded from a text-book diagram of a flip-flop. No one would ever do this in reality. A D flip-flop used in real life in VHDL:
entity flipflop is port ( D : in std_logic; CK : in std_logic; Q : out std_logic; notQ: out std_logic ); end entity; architecture rtl of flipflop is begin process(ck) begin if rising_edge(ck) then Q <= D; notQ <= not D end if; end process; end architecture rtl;Also note - no one would ever make such a simple entity. An entity would usually contain code that synthesised to many (possibly 1000s) of flipflops.
I will have to say, you have been the most helpful person on this entire forum. And you were right i did code using a text book diagram of a flip flop which would explain why my circuit wasn't behaving as expected. TY for posting the code for a flip flop too. I really appreciate it :)