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Kinds of analysis using Quartus II

Altera_Forum
Honored Contributor II
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Dear Altruists, 

I am a new user of Quartus II software. I have already used the DE1 board (having Cyclone II processor). I need to know what type of analysis or data can I get from Quartus II software that will be helpful in writing a journal or conference paper. 

 

Can anybody help me?
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Altera_Forum
Honored Contributor II
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There are reports from each stage of the build - Synthesis report - fitter report and timing report. They will all probably come in useful 

 

But you need to be more specific - what kind of information are you looking for?
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Altera_Forum
Honored Contributor II
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Thank you Tricky. You are always so responsive. More specific information such as Number of gates, Power consumption, Area(size), Block diagram. How can I get these information using Quartus II software?

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Altera_Forum
Honored Contributor II
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FPGAs have no gates, so gate count is not available. What you can get is a count of LUTs, registers, ram, multipliers etc used in the design (ie. the basic parts in the FPGA). This is estimated in the synth report and given in the fitter report. In the fit report it also gives these numbers as a %age of the current device. 

 

Power estimation can be done with the PowerPlay power estimator tool : https://www.altera.com/support/support-resources/operation-and-testing/power/pow-powerplay.html 

 

Block diagrams can be found in tools -> netlist viewers ->
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Altera_Forum
Honored Contributor II
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--- Quote Start ---  

FPGAs have no gates, so gate count is not available. What you can get is a count of LUTs, registers, ram, multipliers etc used in the design (ie. the basic parts in the FPGA). This is estimated in the synth report and given in the fitter report. In the fit report it also gives these numbers as a %age of the current device. 

 

Power estimation can be done with the PowerPlay power estimator tool : https://www.altera.com/support/support-resources/operation-and-testing/power/pow-powerplay.html 

 

Block diagrams can be found in tools -> netlist viewers -> 

--- Quote End ---  

 

 

 

Thanks a lot. I need to compile a design which contains 64 input and 64 output lines. Is there any way to assign pins for those in DE1 board?
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Altera_Forum
Honored Contributor II
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You assign pins via the assignment editor (or if you're using schematic input - which I dont really recommend if you want portability you can assign them on the diagram pins) 

The DE1 reference manual will detail what all the pins are connected to so you can connect them up in your design. 

 

I highly suggest you actually try and do a project in Quartus to learn how to use it - or use online training, rather than keep posting on the forums.
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