DDR 2 Controller IP altmemphy how to connect to Nios System

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I have built a system involving a Nios processor, with data and instruction memory mapped to external DRAM, DDR2 memory Controller IP altmemphy has been used. Plan is to write the data from the processor data master port into the memory base of the DDR2 memory from the processor by using the IOWR_32DIRECT(DDR2_0_BASE,0,0x____DATA___); 

and read through the IORD_32DIRECT(DDR2_0_BASE,offset); and read the data later. While mapping the reset, exception and other vectors, data and memory is mapped to a same address i.e., 0x2000000 and others to 0x10000000, 0x11000000. When I generate the Qsys file i get a warning: 1. The address range of the slaves connected to the NIOS II instruction masters exceeds 28 bits. Attemps to call function accross 28-bit boundaries is not supported by GCC and will result in linker errors.  Because i have connected the instruction master of the Nios processor to the "S"signal of the DDR2 controller IP.  Question: *1.Can I map the data and instuction master of the processor to the same address vectors on the DDR2 Memory i.e., 0x20000000 because it wouldnt allow a different vector if i want to use same data and instruction memory.  After Generating the Qsys IP and instantiating the IP and compiling the design, i get few warnings and no errors. I downloaded the design into the FPGA and built a Nios 2 project from base template hello world(with bsp), i replaced the hello world section to IOWR_32DIRECT and IORD_32DIRECT, used printf to display read https://www.alteraforum.com/forum/attachment.php?attachmentid=9272 data in the console, after that I generated proper BSP and compiled the design successfully. Ran a configuration, the processor ran and the console didnt show any results. (PS: Toggled console On/Off yet no results).   *2.Is the command to write and read a location in DDR2 Memory IOWR_32DIRECT, IORD_32DIRECT correct? If not what is the exact command pls provide the syntax.  *3.Kindly specify if there is any fault in the design logically.  *4.Can anyone provide me Working sample of Nios-II and DDR2 controller IP for cyclone III EP3C120F780C7 and micron DRAM MT47H32M16CC-3/MT47H32M8BP-3.  Note:  1.Used Nios-II f. 2.DDR2 Altmemphy for MT47H32M16CC-3. Default settings. 3.System Clock 125 MHz.   I have attached the project files for the detailed reference.     Regards, Sriram (Altera Enthusiast).

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