I have designed custom PCB in which i have interfaced Cycone III FPGA with DDR II SDRAM. In the designing phase, i assigned the pins with FPGA and synthesize the project. The fitting report was successfull. I have designed the Board with this pin assignments.When i bring up the board and perform DDR II Memory controller timing constraints and synthesize the project, it gives the error that DDRII_UDM pin is failed to be assigned in wrong location. I am stuck at that point. I have studied the Altera Cyclone III app notes. In the forum , one of the pupil has said that if u didnot perform masking on write byte, you have to ground them. Is this schame can work for me?Why this error at this stage? If it was wrongly assigned then why its come occur in initial stage?
Have you run the 'parameters.tcl' script? It may be failing due to missing I/O constraints to do with the DDR I/O and not because the pin is fundamentally wrong.You must have run Analysis & Synthesis on your project first. Then, under 'Tools' -> 'Tcl Scripts...' you should have a list of tcl scripts relevant to the IP you have in your design. Run the parameters.tcl script, relevant to the DDR IP in question. This will add 'a load of I/O constraints' (but not specific pin assignments) relevant to the IP you're using. Check the Quartus Constraints File (.qsf) to ensure that running the script has modified it. Cheers, Alex