Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
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DDR IP avalon waitrequest signal is always high

LiMingchen
Beginner
‎10-14-2021 08:19 PM
814 Views

Snipaste_2021-10-15_11-07-50.png

Port0 works normally, and the waItrequest signal of Port1 is always high since power-on.Avalon of DDR3 has timing alarms.Does it have anything to do with this? Or is it for other reasons?

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AdzimZM_Intel
Employee
‎10-19-2021 11:31 PM
756 Views

Hello,


May I know which device that you're used in your design?

Which Quartus version and simulator tool that you're used?


What do you mean by the timing alarms? Is it a timing warning?

If yes, then it will be great to share the timing report.


Regards,

Adzim


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AdzimZM_Intel
Employee
‎10-25-2021 01:35 AM
709 Views

Hello,


May I know any update on this topic?


Regards,

Adzim


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