Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

DDR SDRAM connection to FPGA

Altera_Forum
Honored Contributor II
1,312 Views

Hi, 

 

I'm trying to design a board for EP3C16Q240C8N FPGA and MT46V16M16P DDR SDRAM. I have read some application notes which say that I have to connect SDRAM data lines to DQ/DQS blocks. My selected FPGA has 4 blocks of x8 DQ/DQS pins, but they are placed each on other side and bank of chip. So my question is - is it OK, to connect SDRAM data pins to two x8 DQ/DQS blocks which are placed on different sides? 

Thanks! 

 

 

Janis
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
599 Views

Yes, it is OK to do so. 

Beware that you only can connect the DM pins on the Top and Bottom bank.
0 Kudos
Altera_Forum
Honored Contributor II
599 Views

Thanks josyb!

0 Kudos
Reply