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DDR output buffer and LVDS pins

Benjamin182
Beginner
977 Views

Hi guys,

 

I've got a question. I need to output a gated LVDS clock (I know gated clocks are bad). On my MAX10 FPGA, I was planning on using a DDR buffer configured like this

ddr_output_DUMMY : ddr_output
port map (
outclock => CLK_100M_PLL,
DIN => "01",
pad_out(0) => CLK_O,
ACLR => '0',
oe => Clock_enable
);

However, I cannot connect a DDR output buffer to an LVDS pair of pins. Is this supported on the Cyclone 10 or Arria 10?

Or is there another "clean" way to gate an LVDS output clock?

Regards

 

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EngWei_O_Intel
Employee
940 Views

Hi there

 

You may refer to link below to better understanding the implementation and design guideline of clock gating.

Recommended Design Practices, Quartus II Handbook (intel.com)

 

Thanks.

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Benjamin182
Beginner
929 Views

Thanks for the reply, but the clock needs to be output from the FPGA to an ADC. And the clock needs to be gated, that's how the ADC is designed. 

https://www.analog.com/en/products/ad7961.html

How should I do it with a Max 10 FPGA?

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