Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
21592 ディスカッション

DDR2 External Memory Interface

Altera_Forum
名誉コントリビューター II
1,057件の閲覧回数

Hi, 

I want to test one DDR2 memory using the example with ALTMEMPHY megafunction on cyclone IV, it compiles without errors or critical warnings, but when I use the ALTMEMPHY External Memory Interface Debug Toolkit it stops at the stage "Read resynchronisation phase calibration", anyone knows how to solve this?, 

Thank you.
0 件の賞賛
1 返信
Altera_Forum
名誉コントリビューター II
346件の閲覧回数

I've read from the uniphy doc that calibration failure at the read stage usually involves problem with address/command clock phase and address/command board skew and delay. what numbers did you use for those parameters?

返信