DDR2 VREF problem

Altera_Forum · ‎12-25-2015

Hi,

My FPGA design uses 4 ddr2 devices. And I use LP2996 to output VTT and VREF for FPGA and DDR2. However, VREF measures 1.43V other than 0.9V. After I cut the VREF output trace, I found LP2996 work well.

I guess the problem is with the FPGA VREF output. I didn't debug all the 4 DDR2(64 bits) but only one(16 bits). So the FPGA pin assignments is incomplete. If a bank doesn't use a voltage-referenced I/O standard, then VREF pins are NOT used as the voltage-reference pins, but common I/O pins. The voltage input of these banks is 1.8V, and the voltage ouput of these VREF pins(not assigned as VREF) is 1.72V(nearly 1.8V). Is it likey that this problem is caused by incomplete pin assignmets?

P.S. The FPGA unassigned pin's output is the same as the bank voltage?

Best Regards,

Cycad Hsu

Altera_Forum · ‎12-25-2015

You may have made the same mistake I did a couple of years ago. The pin labeled VREF on the LP2996 is NOT the pin that gets connected to VREF on the FPGA. It is for capacitor bypassing only. Pins VTT/VSENSE on the LP2996 get connected to the FPGA VREF pins.

Altera_Forum · ‎12-26-2015

However, LP2996 datasheet says that "VREF provides the buffered output of the internal reference voltage VDDQ / 2. This output should be used to provide the reference voltage for the Northbridge chipset and memory. Since these inputs are typically an extremely high impedance, there should be little current drawn from VREF. For improved performance, an output bypass capacitor can be used, located close to the pin, to help with noise. A ceramic capacitor in the range of 0.1 μF to 0.01 μF is recommended."

Actually, both VTT and VREF pins on LP2996 ouput VDDQ/2, but they serves different functions. I'm not sure whether my problem is the same with yours.

Altera_Forum · ‎12-26-2015

I'm not sure either, but if you can lift a pin and add a jumper on the LP2996 you can run a quick test.

Altera_Forum · ‎12-26-2015

Check that you're not exceeding the current capacity of the vref output. The rating on the regulator is probably very low and the total current draw on the FPGA could be higher.

Also if the pins are dual function then be sure to make the assignment. The default is usually input with weak pullup which would inject vddq into the vref through a resistor.

Finally check that there are not any shorts between vref and vddq.

Altera_Forum · ‎12-27-2015

It's the problem of incomplete pin assignments. I debug all the 4 DDR2 devices, and the VREF pins on the LP2996 work well.