Restricted Fmax

[Altera_Forum]

Hello. 

  I am using Quartus II v13sp1 WebEdition. Synthesis is performed for FPGA Cyclone II.   As a result of simulation of any projects (both simple and complex) with the clock frequency greater than or equal 320 MHz system simulation output port is shown constant zero. At frequencies less than 320 MHz simulation system is working properly. Restricted Fmax = 420MHz.   As a simulation system used ModelSim Altera Starter Edition. When using the Quartus II Simulator that is no problem.   Tell me how to solve this problem?

[Altera_Forum]

Another quiz show ... 

It is difficult to say more from your post.  If timequest analysis perfomed right and it was reported such high Fmax properly and gate-level simualtion perfomed in different tools and you are expecting the same result from both tools then ask : where is right model? Did I get your question? If not, please make it clear.

[Altera_Forum]

What is the simulator resolution you have got set? the default is 100ps iirc.  

 But why are you trying simulation at different clock speeds? simulation is mostly used for functional simulation/bug fixing where you are simulating your code (not a gate level netlist) so the clock speed is unimportant. Surely you know what your target clock rate is based on data throughput requirements or available clocks on the board? If you meet this clock speed in timing analysis then you should be good to go (assuming you followed good practice, have good timing constraints)  Simulating at different clock speeds is not really going to be very benefitial.

[Altera_Forum]

Let's look at the problem, about which I wrote earlier on a very simple example - an 8-bit counter lpm_counter. 

Using Quartus 13.0sp1 Web Edition. Device Cyclone II EP2C35F672C6. Fmax = 518.4 MHz Restricted Fmax = 420.17 MHz Clock constraint assigned in value of 420 MHz.  1. Perform functional simulation project using the ModelSim Altera Starter Edition, clock - 420 MHz http://www.alteraforum.com/forum/attachment.php?attachmentid=11622&stc=1  We get the normal simulation results.  2. Perform timing simulation project using the ModelSim Altera Starter Edition, clock - 420 MHz http://www.alteraforum.com/forum/attachment.php?attachmentid=11623&stc=1  We get zero values on the outputs of the counter.  3. However, if you run the simulation time when clock = 420 MHz is not in ModelSim, and Quartus II Simulator - get the normal output value of the counter: http://www.alteraforum.com/forum/attachment.php?attachmentid=11624&stc=1   4. ModelSim Altera Starter Edition shows a non-zero values at the outputs of the counter only if the clock frequency reduced to 320 MHz or less: http://www.alteraforum.com/forum/attachment.php?attachmentid=11625&stc=1   How to Decide this problem with ModelSim simulation at a frequency of at most 320 MHz?  Thanks

[Altera_Forum]

You still havent answered the question - why do you care? What is the target system frequency? Is this just a thought experiment? 

Doing the compilation of a lpm_counter in isolation is going to give much better results than a much fuller FPGA.

[Altera_Forum]

My project is a pipeline scheme - the multiplication of two n-bit numbers. The scheme consists of n-bit registers A and B of the multiplicand and the multiplier, a group of n elements AND, and vertical adder SM. 

 I need to know how long it takes from the receipt of the input data into the input registers scheme to get full results at the output. How do I estimate this interval using Quartus?

[Altera_Forum]

It will take N clocks - where N is the length of the pipeline. Searching through rediculous high FMax is not going to factor in here - you should already know the clock you have. 

Why do you need to know how long it will take? latency shouldnt be an issue - throughput is more important.

[Altera_Forum]

I'm doing research on a pipelined multiplier with a different number of bits according to the complexity,  

throughput and power consumption. I need to find the time during which a multiplier receives the result  of the multiplication of numbers at the highest speed of the device (at the maximum possible frequency).  how this characteristic is changed depending on the number of bits?

[Altera_Forum]

THe cyclone 2 has 18bit x18bit embedded multipliers. So as long as each number is less than 18 bits, then the FMax of the multiplier wont change. 

But if logic is required outside the multiplier, the higher the number of bits the lower the fmax.

[Altera_Forum]

Dear Administration Forum (moderator), please move my topic to the section of Quartus II and EDA Tools Discussion. 

 My topic deals more with issues of work Quartus.  Thank you.