Very fast clock output for Stratix II

[Altera_Forum]

Hi, guys. 

 I'm trying to create a fast output clock using a Stratix II which should feed a measurement device. I'm using the HMX1-AS2 and Hpe_midi boards. The goal is to achieve clock frequencies up to 500MHz and output this clock for a certain number of cycles. (Which is quite optimistic, I have to admit. But the faster the better.) Furthermore the frequency (100MHz, 200MHz, 300MHz, 500MHz) and the number of cycles should be set at runtime. So reconfigurable PLLs seem to be an option for changing the frequency and some simple counting logic should do the clock gating. Although I'm already stuck at the stage of getting a PLL to this speed. So probably this is a bad approach?!  Using a PLL with the given hardware I can reach only little over 200 MHz. The PLL is fed with a 100MHz clock and should be output to an external device. Tuning the PLL to 250MHz or faster will make the TimeQuest Timing Analyzer unhapy for the "Slow Model": (Clock: pll_inst|altpll_component|pll|clk[0], Slack: -1.076, End Point TNS: -30,899) Also a maximum frequency of 226MHz for that clock is stated in the Fmax Summary. I'm using Quartus 13.0.1. since it is the most recent version supporting Stratix II.  So this is it? The PLL can't reliably go faster than 226MHz for the selected device? Or do I overlook something? Did someone here use a higher frequency on a comparable device? (I know this frequency might be enough for most purposes, but I'd need something faster than that.)  Is using the PLL simply a wrong approach for this task?  Also I read that transceivers might do the trick. http://www.alteraforum.com/forum/showthread.php?t=49060&highlight=high+speed+pll Although as far as I know only the Stratix II GX has them, not the Stratix II.  Any other thoughts? I'd be happy for any hint.