DDR2 and DDR3 SDRAM High-Performance Controller

[Altera_Forum]

Dear all; 

 Can I use Debug Toolkit for DDR2 SDRAM High-Performance Controller when DDR2 is controlled by Nios II processor?   Can someone tell me how to use it if the answer is possible? I will appreciate if someone can reply me asap.....   Thanks. Best Regards, Dave

[Altera_Forum]

Yes you can, the debug gui has its own interface when enabled and is completely separate to the local side interface.

[Altera_Forum]

Hello std logic, 

 Thanks for you answer.   I am not clear about your answer. Can your clarify it?   Also, can you provide/describe a simple design which is using nios II to control the debug GUI?

[Altera_Forum]

Sorry, I thought you meant the controller data is coming from Nios. The Debug GUI cannot connect to and be controlled by Nios as far as I am aware.

[Altera_Forum]

Out of interest, what are you trying to achieve?

[Altera_Forum]

Hello std logic, 

 Sorry confusing you. In fact, I should make it clear. Actually, I am beginner of using ddr2 IP & nios II. I plan to use nios II to write/read data from ddr 2 controller. To use the toolkit, I need to instantiate the JTAG Avalon port & debug port into the example top level auto generated file as described in this document (http://www.altera.com/literature/hb/external-memory/emi_debug_hw.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=debug%20tool%20kit%20ddr2 (http://www.altera.com/literature/hb/external-memory/emi_debug_hw.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=debug%20tool%20kit%20ddr2)) pages 4-4 to 4-5. The document does not tell how to write/read data from ddr 2 controller. Is it possible to do it? If yes, can you provide me the guide on how to do it?    Where should I instantiate the JTAG Avalon port & debug port after adding nios II into the project? Is it the instatiantion file (.vhd) generated by SOPC builder?   Thanks. Best Regards, Dave.

[Altera_Forum]

Here is a link to the entire EMI handbook.  

http://www.altera.com/literature/lit-external-memory-interface.jsp  How to read and write to the controller is explained in Volume 2 section 1 for DDR2. Its a standard avalon interface. When you generate the IP you get an example driver which via simulation can show you the required patterns as well.  The debug gui is completely separate thing for debugging your external memory interface and does not connect to the controller or the SOPC bus that you would connect Nios to, its on its own interface. I would not bother with this interface until you well understand the controller and PHY. If you you require this because your HW is broken and you need to debug, yes you can access this debug gui and nios via JTAG at the same time. The debug chapter you mention explains exactly where to add the required files. What is not clear here?  If you are debugging to this level I would first remove your nios driver and just use the example_top design provided when generating the IP.  I hope that all makes sense.

[Altera_Forum]

--- Quote Start ---  If you are debugging to this level I would first remove your nios driver and just use the example_top design provided when generating the IP.  --- Quote End ---   This is what I'm trying to do, but this error appears when compiling the project: "Error: Node instance "altmemddr_0_inst" instantiates undefined entity "altmemddr_0"" What shall I do ?