DDR2 pin placement Cyclone 3 HPC II

[Altera_Forum]

Trying to meet the (absurdly tight) layout requirements for (32 DQ) DDR2 ram on Cyclone 3. HPC II. The layout engineer keeps trying to move pins (within the x8 DQ groups) and the resulting pin map won't route in Quartus.  

 I understand that the assigned DQ/DM/DS pins are "preferred" yet "treated equally by the Quartus router" but there seem to be some arrangements of pin groups that do not work at all. Is there some further guidance on this from Altera? An ap note or something? The iterations are time consuming.

[Altera_Forum]

What error are you receiving? Getting them into the x8 DQ group is the normal issue, but pin-swapping within that normally is not.

[Altera_Forum]

"Critical warning: Fitter could not properly route signals from DQ I/Os to DQ capture registers because the DQ capture registers are not placed next to their corresponding DQ I/Os" 

 Maybe not fatal, but not something to blindly push past, either.  EP3C120F484I7  dq23 = A18 dq22 = A16 dq21 = D19 dq20 = F15 dq19 = E15 dq18 = E16 dq17 = C17 dq16 = C19 dm2 = A17 ds2 = F13  If I swap A17 and A18, the fault goes away, which is surprising because it is actually A16 that is preferred for DM2.  There are other swaps that cause this fault, but I don't have the data. Some of the other issues I've seen are now understood as our error.

[Altera_Forum]

Not sure. I would look at where the DQ capture registers are placed. Maybe there are too many going into a LAB or something like that?