Dear All,
I have a problem with sharing of DDR2 memory between the Nios program and the rest of the SOPC builder components which access the DDR2 either. More precisely 2 Frame Buffers from the Video IP suite.
Therefore I have a problem in the Nios2IDE:
Verify failed between address 0x40000000 and 0x4000D9E7
Leaving target processor paused
Does anybody can give a gudeline how to specify offsets to share the DDR2 memory between several devices?
I use Nios_f with instruction cache 4K and data cache 2K.
The size of my software is around 24K. I'm specifying offset for reset - 0x0 and excetption vector - 0x2.
Actually, I had 2 versions of my HW/SW.
In the first version only Nios II processor and one Frame Buffer accessed the DDR2.
I set the offset for the Frame buffer as 0x00050000.
And my software run successfully - no problem.
In the second version I added the second Frame Buffer. All setting for Nios are same. I've changed only Frame Buffer1 offset to 0x00080000 and have set offset for the Frame Buffer2 - 0x20000000.
And after that I'm starting to get my memory verification error.
Can anybody suggest what I do wrong?
BTW the SOPc builder writes that the size of my 2-nd Frame Buff is 12289Kb and 1-st is 16561KB.
The external memory used is Hynix H5PS5162FFR-16C (DDR2-600 512Mb x16).
Any help is very appreciated.
