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Altera_Forum
Honored Contributor I
784 Views

DDR3 HMC Timing issue with Qsys(device:5CGXFC5C6F27C7)

I'm a beginner in FPGA. project contains DDR3 Hard memory controller and Avalon-MM Traffic Generator, the HDLs and sdc is generated by Qsys. 

 

but timeQuest show timimg closure errors. why? 

 

is there a risk in using the cyclone V ddr3 hard ip?  

 

thanks in advanced 

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10107&stc=1  

 

http://www.alteraforum.com/forum/attachment.php?attachmentid=10108&stc=1
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2 Replies
Altera_Forum
Honored Contributor I
36 Views

Have you got the solution? maybe I met the similar problem with you.

Altera_Forum
Honored Contributor I
36 Views

Simply means you are trying to clock everything too fast for the FPGA speed grade. The combinational paths will be too long to allow timing closure. 

 

The answer is to either reduce the clock frequency, or reduce the design complexity, or add additional pipelining in long paths. The latter two are not really possible with closed IP cores, unless you can get away with adding a pipeline stage between the traffic generator and the DDR3.
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