DDR3 SDRAM controller core

[Altera_Forum]

I am working on Cyclone V project (5CEFA5F23C8) and I have DDR3 SDRAM controller core instantiated. 

I am getting hold violations for the DDR_DQ path. I have seen in the qsys that constraint scripts would be applied but not able to see those constraint scripts in sdc file. Does anybody know where these scripts are generated so that I can copy paste to my top sdc file.

[Altera_Forum]

If you're using Qsys, they are supposed to be added automatically. Do you have unconstrained inputs/outputs or clocks elsewhere that could be adding to this?

[Altera_Forum]

I assume you are talking about the TCL files created when a QSYS design generates files. These files should not be added to your project in any way. They are not part of the project, but when run they add settings needed for proper operation of the memory controller. 

 When you generate files from QSYS, a message is shown telling you what script you need to run. Back in Quartus, you need to use the "Tcl scripts..." command in the tools menu to run the script the QSYS message told you to run.

[Altera_Forum]

--- Quote Start ---  I assume you are talking about the TCL files created when a QSYS design generates files. These files should not be added to your project in any way. They are not part of the project, but when run they add settings needed for proper operation of the memory controller.  When you generate files from QSYS, a message is shown telling you what script you need to run. Back in Quartus, you need to use the "Tcl scripts..." command in the tools menu to run the script the QSYS message told you to run.  --- Quote End ---    I'm actually talking about the SDC file that you mentioned-- If it is in the QIP file, then it should be read by Quartus. Otherwise it might need to be added manually in the SDC file list. Otherwise-- I'm not sure as I'm currently working on a board with no FPGA-based DDR, and can't remember the process. I'm sure someone else can chime in on that.

[Altera_Forum]

In your top post you say "I have DDR3 SDRAM controller core instantiated" and in the lower post "I'm currently working on a board with no FPGA-based DDR" Which is it? In regards to the constraints, the tcl script adds them to the project when it's run. No sdc file is created.

[Altera_Forum]

--- Quote Start ---  In your top post you say "I have DDR3 SDRAM controller core instantiated" and in the lower post "I'm currently working on a board with no FPGA-based DDR" Which is it? In regards to the constraints, the tcl script adds them to the project when it's run. No sdc file is created.  --- Quote End ---     Different posters, Galfonz.

[Altera_Forum]

Well I sure botched that one...

[Altera_Forum]

Thank you GalFonnz. Do you mean to say that whatever parameters I input in memory timing and board settings tab during DDR3 instantiation are automatically taken care of? How to check whether those constraints are applied as I dont see any SDC generated for DDR3 core as a seperate file.

[Altera_Forum]

Nothing is automatically taken care of. DDR is highly dependent on board geometry. To the point that I just take the settings from example projects for the board in question. I don't have any experience in DDR design, it's a complex topic that I don't have time/desire to learn, or the expensive PCB software that would make it possible for a beginner to have any confidence in a DDR design.