DDR3 Timings Violation - MAX10 NEEK

[Altera_Forum]

Hi there, 

 I tried building a design example (downloaded from the altera cloud service) which is using the DDR3 UniPHY based memory controller. However, if compiled as it is without any changes the TimeQuest analyzer reports violations on the DDR bus. For example I compiled lcd painter using Quartus ver. 15.0. I noticed that the other examples that I tried with DDR3 also have timing violations. I tried some compiling optimizations but still have the issue. I checked also that the .sdc file is after the .qip in the file list.  I'm thinking of some global Quartus setting that could probably effects this (if we suppose that it timings should be ok with this design). I'm using 15.0.0 Build 145 04/22/2015 SJ Web Edition.  If somebody has any suggestions?  Thanks in advance, Victor

[Altera_Forum]

Try using more aggressive performance optimization

[Altera_Forum]

Even the most aggressive optimization gives timing violations. Strange...

[Altera_Forum]

Maybe you have to review reset network created by qsys or fine-tune the system for q15

[Altera_Forum]

Check if the violations were reported at unusual conditions of voltage and/or temperature. The default timequest settings perform analysis at several temperature and voltage settings. If you get violations only in unrealistic (for your project) conditions, check the results for the typical environment. If it's OK there, you can ignore the violations but be aware your design won't work in the more extreme conditions. 

 Edit: Many of the Altera samples and demos are like this.

[Altera_Forum]

I did a lot of experiments with the Quratus settings, however no result. I'll try to get deep in the qsys output and the generated memory module. 

 Galfonz, i'm not sure how the models of the physical device are implemented. Is there a way to set a specific temp for the simulations? From what I see in the qurtus settings I can only disable and enable the mulcticorner timing analysis (best/worst conditions).  Thanks for the replies. Victor

[Altera_Forum]

The timequest documentation describes how to create and edit configurations for doing analysis. Also see volume 3 (verification) of the quartus handbook. The default is to use I think 3 different configurations for the analysis.

[BDarji]

Hello,

Although it is too late, this might be helpful to someone in future.

Answer given in following post helped us to close timing for DDR3 design on Max 10 development kit. 

https://community.intel.com/t5/FPGA-Intellectual-Property/Recovery-violations-uniphy-DDR3/m-p/141584/highlight/true

Thank you.