DDR3 Uniphy altera example design error in Modelsim

[Altera_Forum]

Hi, 

I'm trying to simulate the DDR3 Uniphy Memory controller example design in Modelsim, but I keep getting errors. I did everything Altera said in its readme.txt file. Nothing helps... In Modelsim I compile the run.do file of ALtera and after a while see: # ** error: (vcom-1935) unable to move temporary file c: /cccc/coresddriiiuniphy/ddriiiuniphy_example_design/simulation/vhdl/mentor/libraries/work/_temp/vlog6rajn8 to c:/cccc/coresddriiiuniphy/ddriiiuniphy_example_design/simulation/vhdl/mentor/libraries/work/ddriiiuniphy_example_sim_e0_if0_s0_mm_interconnect_0_cmd_xbar_demux_001/_primary.dbs.#  # no such file or directory. (errno = enoent)  Did anyone have this error? How to get pass it? Thx

[Altera_Forum]

Can I assume you copied and pasted the error message into the post? I can't help but notice the "space" in the path of the source file. "c:_/cccc/...". Is it that the tools can't find the source file? 

 Cheers, Alex

[Altera_Forum]

No... I just deleted my computer details. :o)