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Valued Contributor III
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DDR3 calibration fail (Cyclone V + Micron DDR3 + Uniphy + NiOS)

Dear All, help me please in a trouble. 

 

I have a custom board with cyclonev (including Hard-IP DDR) and DDR3 (mt41j128m16jt-125). In quartus ii v14.1.0 (64bit) I created SoC (NIOSII + block ram + hard SDRAM Uniphy controller + external DDR3): 

http://www.alteraforum.com/forum/attachment.php?attachmentid=12773&stc=1 http://www.alteraforum.com/forum/attachment.php?attachmentid=12774&stc=1  

 

Program for NIOS loaded from the internal block RAM and should check DDR3 memory. But all hangs after attempting DDR3 memory access (before it code is running ok). It seems that DDR calibration fails. Signals local_init_done and local_cal_success are deasserted. The local_cal_fail is asserted. 

 

RTL testbench generated by QSYS works fine (local_init_done and local_cal_success asserted, local_cal_fail is deasserted, I can see transactions). 

PLL in memory controller is locked (pll_sharing_pll_locked is asserted on real board). 

External Memory Interface Toolkit can see memory and able to connect (so Avalon transactions is ok?). In this tool I can make memory reset. After this local_cal_fail is deasserted for the moment and then asserted again. External Memory Interface Toolkit reports told that calibration fails at the stage write calibration - per-bit write deskew failure

 

Memory frequency is 400mhz. I obtained timing settings from presets for mt41j128m16ha-125 (my chip is mt41j128m16jt-125 but they differs only by the type of package, isn't it?). 

The board settings for this custom board is unknown. So I leave default values. 

 

Actually I have two x16 DDR3 mt41j128m16jt-125 chips connected to my FPGA with the same address and command buses. But I connected to DDR3 controller only one of these chips. So the DDR3 controller drives address and command bus of another memory chip but not the data. May it be an issue?  

 

Thanks in advance for any kind of help!
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Valued Contributor III
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Hi, when you generate the Qsys design, try choosing the create simulation model as "none"

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Valued Contributor III
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--- Quote Start ---  

Hi, when you generate the Qsys design, try choosing the create simulation model as "none" 

--- Quote End ---  

 

It doesn't help :(
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Valued Contributor III
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Perhaps you can check the link below: 

http://www.alterawiki.com/wiki/uniphy_external_memory_interface_debug_toolkit 

 

calibration failure can be caused by a lot of different possibilities so unfortunately you'll have to narrow it down
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Valued Contributor III
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Unfortunately there could be many cause to a calibration failure - you can refer to the link below and try to isolate the symptoms: 

http://www.alterawiki.com/wiki/uniphy_external_memory_interface_debug_toolkit
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Valued Contributor III
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Hi samuray, 

 

we are using the same memory in a cyclone5 design. It works fine. Actually we have just one memory device. The hardware release before which had two devices with shared address/command bus and a 2 x 16 bit data bus also ran properly. 

I think both designs use the same UniPhy settings. I will attach my current setting. 

 

Jens
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Valued Contributor III
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and here is the 6th page ...

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Valued Contributor III
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Thank you so much, Jens! You helped me a lot!  

With your settings it started to work.  

Then I changed soft controller to hard, increased memory frequency up to 400 MHz and changed tWTR from 7 to 6. And It still working! 

Thanks a lot for your help!!
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