DDR3 interfacing with Cyclone V E device

[Altera_Forum]

With this Cyclone V E device, what is the maximum DDR3 memory capacity I can interface to? 4 GB or 8GB?

[Altera_Forum]

The FPGA itself does not care about how much memory you're accessing. It depends on the board.  

The only limitation I see is if you try to use it with a NIOS processor, which is 32-bit limited and uses the upper bit for non-cached access. And because the address space is shared with the other peripherals, effectively 1GB.  But you could split this 1GB into "banks" or perhaps chunk it to 8 other NIOS. But the device itself can handle whatever.

[Altera_Forum]

what is the DDR3 size you wish to implement?

[Altera_Forum]

I wish to implement 2GB DDR3 memory with Cyclone V E device (5CEFA523C8N). I am planning to use hard memory controller interfaced to NIOS II/s. But I am not sure if controller supports 2 GB? 

 Please help me!

[Altera_Forum]

how about you have try to configure a 2 Gb and see if the compilation able to get pass with no error..