DDR3 uniPHY Controller Cyclone E - differences between Hardcore and Softcore

[SDavi9]

We have a design using the DDR3 Hard Core Memory Controller with UniPHY implemented within a 5CEFA7U19I7N. I would like to know if we could use a 5CEBA7U19I7N - this would mean changing from a Hardcore to softcore. What are the major differences between the Hardcore and Softcore ? Would this require for a new pinout and thus a new PCB design ? 

Thank you in advanced for all your help

[AdzimZM_Intel]

Hi Sdavi9,

Thank you for using Intel Community.

I'm Adzim from Penang Global Application Engineer.

I will assist you in this thread.

The major difference between the hardcore and softcore is that the availability of memory controller design block.

In hardcore, there is a design block that can be used as memory controller.

While in softcore, this block is not provided. So user must create their own soft memory controller.

When the user has setup their own soft memory controller, it's can be connected to soft PHY only.

The Hard PHY can only be used with hard memory controller.

The pinout can be remained if the interface is similar. Make sure that the soft memory interface can fit with hard memory interface.

The maximum memory frequency for softcore is lower than hardcore which is 303MHz with half-rate mode.

Please let me know if those information is helping you.

Thanks.

Regards,

Adzim

[SDavi9]

Dear Adzim,

Thank you so much for getting back to me. 

Do you have any information of how I would create this "soft memory controller" in such a way that I could use it with the same pinout that we have designed 5CEFA7U19I7N so that we can move to a pin to pin replacement using the 5CEBA7U19I7N  with no need for a re-spin of the PCB ? 

You mentioned that the softcore frequency issue. Are you able to provide more details of how much of a reduction I would be looking at ?

Best regards

Shmuel  

[AdzimZM_Intel]

Hi Shmuel,

You can use the UniPHY Hard Memory Controller as a reference to create your own soft memory controller block.

Please refer to Cyclone V Device Handbook for more details.

https://www.intel.com/content/www/us/en/docs/programmable/683375/current/external-memory-performance.html

Thanks,

Adzim

[AdzimZM_Intel]

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