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Altera_Forum
Honored Contributor I
738 Views

DDR3L interface query

Hi, 

 

As mentioned in the below schematic, we are using banks 7A and 8A of Cyclone V (5CEFA5F23C8) to interface to DDR3L memory device. For bank 7A, we are providing the voltage of DDR3L and we have grounded the bank8A voltage pin. 

 

Is this configuration valid?
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2 Replies
Altera_Forum
Honored Contributor I
40 Views

check io standard in bank8a, if all io doesnot reference voltage, you can connect it to gnd or vccio in the bank.

Altera_Forum
Honored Contributor I
40 Views

VREF is only needed for inputs. Since all of the signals in your bank 8A are address/control outputs (except for the diff clock input) I'm 99% sure you're fine to tie the VREF pin to GND. Read the handbook and pin connection guidelines to make sure.

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