As mentioned in the below schematic, we are using banks 7A and 8A of Cyclone V (5CEFA5F23C8) to interface to DDR3L memory device. For bank 7A, we are providing the voltage of DDR3L and we have grounded the bank8A voltage pin. Is this configuration valid?
VREF is only needed for inputs. Since all of the signals in your bank 8A are address/control outputs (except for the diff clock input) I'm 99% sure you're fine to tie the VREF pin to GND. Read the handbook and pin connection guidelines to make sure.