Hi!I am looking to design a simple processor using an Altera DE0-Nano Board. I focus on energy efficiency so I want to incorporate Dynamic Frequency Scaling to my design. Upon my research, many mention that if I just scale the frequency but not change the core voltage, I will just be wasting power. I already have different frequency levels at 50MHz, 40MHz, 30MHz and 20MHz made with Altera MegaCore PLLs but I do not know how to vary the FPGA's core voltage. Will just using the different frequency levels save me power even if I just use a constant core voltage? If not, what should I do to correctly implement Dynamic Frequency Scaling on the DE0-NANO Board? I have uploaded the schematic with this post. I desperately need help. TIA.
The DE0-Nano board uses a Cyclone IV E device. There are two flavors of the IV E family: N = 1.2V core voltage (VCCINT), L = 1.0V core voltage.The DE0-Nano board uses a N device (1.2V). If you want lower power find a board with a L device. But for either device the VCCINT voltage is fixed (+/- 3-4%), so you can't vary the core voltage from nominal any appreciable amount. If you tried you may trip the internal POR circuit, although I don't know what the POR thresholds are. The DE0-Nano board doesn't support varying the core voltage anyway, so varying clock frequency is all you can do on this platform. Good luck with your project. Bob