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Altera_Forum
Honored Contributor I
813 Views

DDR3SDRAM IP-core, number of chip selects

hello everyone. 

 

I am trying to create DDR3-IP core. 

I want to connect two DDR3-SDRAM SODIMMs(64bits) in parallel. 

 

each SODIMM has two chip selects pins. 

so the case needs four chip selects. 

 

I try to do so in QuartusPrime 15.1. 

but I only can select two chip selects.( see attached file ) 

 

I think old version of QuartusII could set bigger number, because in that time I set the number directory. 

 

how can I set lager number? or can't I do that?
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9 Replies
Altera_Forum
Honored Contributor I
28 Views

> because in that time I set the number directory. 

this was not true, in that time (QuartusII 12.1) you can choose 1,2,4,8. 

 

sorry.
Altera_Forum
Honored Contributor I
28 Views

Which device are you using? You may need to create two separate instances of the IP.

Altera_Forum
Honored Contributor I
28 Views

hello sstrell 

thank you. 

 

I am using CycloneV (5CGXFC9...) 

if I need to create two separate instances, which means that data bus can not be shared right? 

I don't have enough pins for the second IP.
Altera_Forum
Honored Contributor I
28 Views

If you're using the hard IP, take a look at the ping pong Phy feature to share address and command pins.

Altera_Forum
Honored Contributor I
28 Views

I think ping pong PHY is not for cycloneV. 

I could find ping pong PHY for Arria10 but not others ( I mean cycloneV, ArriaV )
Altera_Forum
Honored Contributor I
28 Views

I'm pretty sure that if you use the hard IP (not the soft controller) in Cyclone V, you can use ping pong phy. Try adding the ip and check the parameter editor for the option.

Altera_Forum
Honored Contributor I
28 Views

Whoops, just looked it up: Arria V GZ and Stratix V only (for pre-Arria 10 devices).

Altera_Forum
Honored Contributor I
28 Views

Things are clear thank you anyway

Altera_Forum
Honored Contributor I
28 Views

I believe Cyclone V doesn't support DDR3 write leveling, so no chance to use DDR3 SODIMM modules.

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