Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
Need Forum Guidance? Click here

Search our FPGA Knowledge Articles here.
19335 Discussions

HPS SPI remapped to FPGA cause system hangup

Altera_Forum
Honored Contributor II
863 Views

Hi all! 

 

Up untill now I've successfully used SPI master remapped to FPGA pins with CS pin via PIO. In my u-boot.scr I had such coded: 

fatload mmc 0:2 $fpgadata UniDAS.rbf; fpga load 0 $fpgadata $filesize mw $axibridge ${axibridge_handoff}; mw $l3remap ${l3remap_handoff}  

Now I'm trying to enable FPGA to HPS SDRAM bridge so I change code to this: 

fatload mmc 0:2 $fpgadata UniDAS.rbf; fpga load 0 $fpgadata $filesize run bridge_enable_handoff;  

With system console and JTAG-to-AvalonMM I verified that bridge is working fine. But! Now when I try to send data over SPI (via Linux spidev) Linux hangs and reboot. U-Boot and Preloader are both updated to match firmware. 

Connections: 

https://alteraforum.com/forum/attachment.php?attachmentid=15439&stc=1  

 

Maybe any one has clues what it may be?
0 Kudos
2 Replies
Altera_Forum
Honored Contributor II
119 Views

Is it only I or screenshot is broken? Anyway - new link: https://imgur.com/a/9mfmedw

Altera_Forum
Honored Contributor II
119 Views

I've replaced u-boot.scr code with this: 

fatload mmc 0:2 $fpgadata UniDAS.rbf; fpga load 0 $fpgadata $filesize mw $axibridge ${axibridge_handoff}; mw $l3remap ${l3remap_handoff} mw $fpga2sdram ${fpga2sdram_handoff};  

 

and verify that JTAG master can read system memory and SPI do not hang the system. But I do not know why this is happening.
Reply