I am using the qts_hilo_ddr4_x72_1066MHz sample project to test the DDR4 HILO in the Stratix 10 MX development kit. I didn't change anything, except upgrading the project from Quartus 18.1 to Quartus 19.4.
After downloading the SOF file in the board, I used SignalTap to observe the signals and realized that DDR4 HILO controller module always returned local_cal_fail = 1.
Please find the sample project attached and let me know how I can fix the issues.
Thank you very much,
Below action can be implement to see if anything help.
1. You can use the original qts to test, no need to update.
2. Lower the EMIF clock frequency to 933Mhz.
3. Disable address/command calibration step one by one shown as below.
Hi @ybin ,
Thank you for your response.
1) I am using Quartus pro 19.4 in our system. The HILO module will need to be integrated into our system later. Therefore, I don't see any reason to downgrade the Quartus from 19.4 to 18.1 just for testing for memory module.
2) The example design is using 1066 MHz. Does lower EMIF clock to 933 MHz mean the example design was not correct?
3) The example design already disabled that setting.
To lower the frequency is just to have a test, to see if lower frequency is effect.
To disable/skip address/command calibration step is to enable the highlight setting. Pls make sure you follow it. If all the 3 actions you are implement, please let me know the result.
I check the development kit bts setting, I find that the type of DDR4 is UDIMM. Can you check your board's DDR4 type from the part number? To see if it's the same as BTS setting.
BTW, you compiled BTS and test it, not just use the sof from the download package, Is that right?
Besides the question I mentioned before, below two points need to check:
1) Do have any physical inspection being performed on DDR4 hilo card? Ensure you plug in the DIMM properly to avoid bad pin contact issue.
2) Please offer either dev kit or DDR4 hilo card serial number.
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