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Altera_Forum
Honored Contributor I
1,027 Views

DE0-Nano PLL "non-dedicated routing"

Hi there, 

 

I'm having a bit of difficulty getting to the bottom of some warnings to do with the PLL I am using on a Cyclone IV. I'm using the DE0-Nano from Terasic. 

 

The 50MHZ onboard oscillator is connected to PIN R_8, from what I can tell on the pin planner in quartus, this is correclty connected to the PLL input clock. 

 

I have only one output from this PLL, feeding pin R_4, which again on pin planner is marked as "PLL other". (The net on the board is connected to DRAM_CLK, which is what I am working on as I am buiding a SDRAM controller). 

 

When compiling, I get the following error message: 

 

Critical Warning (176598): PLL "PLL_MOD:PLL_BLOCK|altpll:altpll_component|PLL_MOD_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated because it is fed by a remote clock pin "Pin_R8" 

 

All of the threads I've read online usually state that you need to use the correct PLL pins, which I beleieve I am. Not that I have a choice in the matter as it is a development kit). 

 

When I run the DE-Nano examples which use the PLL, they don't have this issue. 

 

Any ideas what I am doing wrong / what I have miss-understood? 

 

I've uploaded the VERY basic project that shows the issue I am having. 

 

Best Wishes 

 

Xander
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3 Replies
Altera_Forum
Honored Contributor I
64 Views

Hi,  

 

You get this warning because:  

Clock from PIN_R8 can directly feed only PLL_4, but you want to use PIN_R4 clock output which is dedicated clock output of PLL_1. So fitter puts your PLL in PLL_1 location to use dedicated clock output and routes clock from PIN_R8 trough GCLK (global clock network).  

 

So there is no way to avoid this warning in your case (unless you change your PLL mode to NORMAl and feed clock output trough ALTDDIO_OUT megafunction). I have worked with DE0-nano SDRAM and I have ignored this warning and SDRAM worked fine for me.
Altera_Forum
Honored Contributor I
64 Views

vlrean, 

 

Thank you for the reply. This was what I was suspecting. What really confuses me is when I use one of the pre-supplied DE0-Nano examples, such as the accelermeter example, and change the PLL output to pin_R4, it doesn't show the error message. 

 

Is it possible they have supressed the message? And do you know where I should be looking to see if this is the case? 

 

Thanks 

 

Xander
Altera_Forum
Honored Contributor I
64 Views

Hi,  

 

Go trough reports.  

1. Fitter->Resource usage -> PLL Usage (you will see what PLL location is used) 

2. In same report location you will found what PLL mode is used.  

3. Fitter -> Supressed messages you will found out if there is any supressed messages.
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