The arithmatic blocks found in the Altera IP suite e.g the LPM airthmatic blocks, have an option for pipelining and achieving latency for a specific number of clk cycles.What is the main purpose of this? Does it always help achieve a higher clock frequency?
There are several reasons:1. Improving timing performance, especially for LPM divide. The latency will improve it up to a point, but making it longer will not likely make improvements. 2. Using dedicated multiplers in DSPs 3. balancing pipelines ie. you have parallel processing pipelines, and you want to make them the same length