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DE0 SDRAM memory

Altera_Forum
Honored Contributor II
‎12-02-2011 12:27 PM
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Hello,  

 

I have a doubt about the connection between de Cyclone III and the SDRAM A3V64S40ETP in my DE0 board. In the datasheet of the SDRAM we have 12 inputs addresses (A0-A11) while in the datasheet of the DE0 pin connections there are 13 addresses specified (A0-A12) between the FPGA and the memory. Which is the reason of this since the SRAM only have 12 inputs! 

 

Thank you
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Altera_Forum
Honored Contributor II
‎12-02-2011 09:46 PM
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the RAM is probably available in a larger density, so the route was made to the MSB in case you or the vendor wants to upgrade the memory chip

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Altera_Forum
Honored Contributor II
‎12-02-2011 11:51 PM
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Thank you for your prompt response! 

 

Josep
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