so i've made a 16mb sdram controller to use as memory for the niosii i made in qsys, qsys is supposed to fix the clock difference itself implicit, so i just connect everything, and then connect the pinouts, compile the hw and load on the DE1-SoC, then the wierd stuff begins.. if i use onboard memory, i can load a sample hello world/nios application and get the output over jtag nios console but if i choose the sdram memory, i allways get errors on verify, which makes be wonder if there is some timing settings errors (i've just used the standard timings as there are no info about that stuff in the manual.. if not that im thinking i need to explicit send a 100mhz clock to the sdram controller cause all the pinouts are correct, so it should work as far as i have understood..
also if i choose more then 1 memory chip, then DRAM_CS_N goes from single element, to multiple elements, and the manual specifies that its supposed to be a 64mb sdram, but also specifies DRAM_CS_N as a single 3.3v signal.. so theres something funny there too.. unless its supposed to be another sdram controller then "sdram controller"...
