DE115 Lab 1 part 2 Question

[Altera_Forum]

can not compile at x <= SW[7:0];, how to fix it? 

 LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY Lab1b IS PORT (  x : IN STD_LOGIC_VECTOR(7 DOWNTO 0); y : IN STD_LOGIC_VECTOR(15 DOWNTO 8); s : IN STD_LOGIC_VECTOR (1 DOWNTO 0); m : OUT STD_LOGIC_VECTOR (15 DOWNTO 0) ); END Lab1b;  ARCHITECTURE Behavior OF Lab1b IS BEGIN x <= SW[7:0]; y <= SW[15:8]; m <= (NOT (s) AND x) OR (s AND y); LEDR <= m; END Behavior;

[Altera_Forum]

First, just look at your code. 

 You have the ports defined using one style of vector syntax, and then the assignment to x using a different sort of syntax. Modelsim or Quartus will tell you which is wrong, as will any book on VHDL.  Now, look at your code again for all the signals in the design; you have x, y, s, and m on the entity - think of this as the pins on the device - now where does SW come from? How about LEDR, where does that go to?  Draw yourself a block diagram of what you want, write signal names in the block diagram, and it'll start to become clear what to do.  Cheers, Dave

[Altera_Forum]

https://skydrive.live.com/redir?resid=e0ed7271c68be47c!298 

https://skydrive.live.com/redir?resid=e0ed7271c68be47c!297  when s = 0, m = x, when s = 1, m = y, i am doing this part of lab 1

[Altera_Forum]

Study Yourself instead of asking here. Or you want to fail Your exams?