Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers

DESign.sof

Altera_Forum
Honored Contributor II
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Hello! 

 

I have a little problem whit a design file, i have a Stratix II board model: EP2S60F672C3 and when i open my design file DESign.sof whit the Programmer in Quartus II i see the file whit other device: EP20K200EF484.  

 

Error: Can't configure device. Expected JTAG ID code 0x082000DD for device 1, but found JTAG ID code 0x120930DD.  

Error: Operation failed.  

These are the errors i get when i try to start this file...  

Id like to know how could i change the device for that file to make that file for my device...  

 

I will apreciate youre help and assitance. 

Thank you!
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Altera_Forum
Honored Contributor II
1,151 Views

 

--- Quote Start ---  

Hello! 

 

I have a little problem whit a design file, i have a Stratix II board model: EP2S60F672C3 and when i open my design file DESign.sof whit the Programmer in Quartus II i see the file whit other device: EP20K200EF484.  

 

Error: Can't configure device. Expected JTAG ID code 0x082000DD for device 1, but found JTAG ID code 0x120930DD.  

Error: Operation failed.  

These are the errors i get when i try to start this file...  

Id like to know how could i change the device for that file to make that file for my device...  

 

I will apreciate youre help and assitance. 

Thank you! 

--- Quote End ---  

 

 

Hi, 

 

how do you generate the design.sof file ?
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Altera_Forum
Honored Contributor II
1,151 Views

In menu: 

 

assignments->device  

 

choose your Stratix II device. 

 

and Compile again.
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Altera_Forum
Honored Contributor II
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Hello Pletz! 

 

Well i didnt generated this file, i have downloaded it from a website. Is there a way i can convert this file to fit on my board? I have started to read on altera website help and learning but it looks like im far away from my interests. The file is part of a des key extractor.  

 

 

 

Hello Parrado! 

 

I have tryed manny times i have started to read on altera website help and documentation regarding Quartus II software and found this, so i have tryed i selected my device but compilation was unsuccessfull all the times manny errors.  

 

I uploaded the files in discussion now so maybe i can get better help. 

I also look on altera video demos on compiling programming and i started learning but at the moment i am in the very beginning phase... from what i understood is that i can design almost any kind of electronics so i have more questions regarding this board... is it posible to use it as a LAN card to my computer? Video card?  

 

Thank you all for youre respnoses!
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Altera_Forum
Honored Contributor II
1,151 Views

A FPGA configuration file can't be converted to another device type, it has to be generated from the original project files. The appended files however aren't a complete project.

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Altera_Forum
Honored Contributor II
1,151 Views

 

--- Quote Start ---  

Hello Pletz! 

 

Well i didnt generated this file, i have downloaded it from a website. Is there a way i can convert this file to fit on my board? I have started to read on altera website help and learning but it looks like im far away from my interests. The file is part of a des key extractor.  

 

 

 

Hello Parrado! 

 

I have tryed manny times i have started to read on altera website help and documentation regarding Quartus II software and found this, so i have tryed i selected my device but compilation was unsuccessfull all the times manny errors.  

 

I uploaded the files in discussion now so maybe i can get better help. 

I also look on altera video demos on compiling programming and i started learning but at the moment i am in the very beginning phase... from what i understood is that i can design almost any kind of electronics so i have more questions regarding this board... is it posible to use it as a LAN card to my computer? Video card?  

 

Thank you all for youre respnoses! 

--- Quote End ---  

 

 

Hi, 

 

I have setup a project for you. Unfortunately the design files are not complete. The Nois is missing, but maybe you can use the project as starting point.
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Altera_Forum
Honored Contributor II
1,151 Views

Pletz 

 

Nois or Nios? You mean Nios II processor? id like to learn making one... :)
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Altera_Forum
Honored Contributor II
1,151 Views

 

--- Quote Start ---  

Pletz 

 

Nois or Nios? You mean Nios II processor? id like to learn making one... :) 

--- Quote End ---  

 

 

Yes, I mean the the Nios II processor. It lookslike that he is used in the tutorial. Is there no description in the tutorial how to generate the Nios II ? I would expect that the required design files are somewhere in the tutorial database.
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Altera_Forum
Honored Contributor II
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I saw Quartus have ed8b10b encoder/decoder, anyone can help me whit this? how to? i have read and follow the steps in /ug-ed8b10b.pdf literature but i have problems loading the libraries. Is there anyone to have this encoder/decoder available? Mail it? :) please.

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Altera_Forum
Honored Contributor II
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For Altera 8B/10B encoder IP core you need to purchase a separate license to use it in your application. It's available for free OpenCore Plus Evaluation as described in the user guide. You can also find free 8B/10B cores at opencores.org.

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