Vhdl?

[Altera_Forum]

Can anyone help with explaining how the statement below works? I'm confused as to why you AND data_out? 

 Is the statement saying   if address = x then  read_mux_out <= data_out  Statement in question ------------------------- read_mux_out <= A_REP(to_std_logic((((std_logic_vector'("000000000000000000000000000000") & (address)) = std_logic_vector'("00000000000000000000000000000000")))), 13) AND data_out;  Thanks for any help Guy

[Altera_Forum]

Hi gicolleta, 

 the statement works right but too complicated to such simplest task :)  1. std_logic_vector'("000000000 000000000000000000000") & (address) - produce 32bit vector from 2-bit address?  2. compare it with 32'h0 and get one-bit result: to_std_logic((((std_logic_vector'("000000000 000000000000000000000") & (address)) = std_logic_vector'("0000000000000000000000000000000 0"))) 3. replicate result upto data_out length vector : REP_A(0/1, 13) 4. Finally just bit-wise AND data_out with '0 or '1 vector - propagate data_out to mux or not.   Alternative:  read_mux_out <= (others => '0') when address = "00" else data_out;

[Altera_Forum]

--- Quote Start ---  Hi gicolleta,  the statement works right but too complicated to such simplest task :)  1. std_logic_vector'("000000000 000000000000000000000") & (address) - produce 32bit vector from 2-bit address?  2. compare it with 32'h0 and get one-bit result: to_std_logic((((std_logic_vector'("000000000 000000000000000000000") & (address)) = std_logic_vector'("0000000000000000000000000000000 0"))) 3. replicate result upto data_out length vector : REP_A(0/1, 13) 4. Finally just bit-wise AND data_out with '0 or '1 vector - propagate data_out to mux or not.   Alternative:  read_mux_out <= (others => '0') when address = "00" else data_out;  --- Quote End ---    Thanks Mixa :)

[Altera_Forum]

Normally, I would refuse to edit such confuse VHDL code. It should be noted, that A_REP isn't a standard VHDL library function, I see that it's defined in altera_europa_support_lib.vhd. It's not clear to me, if it works at all to apply A_REP to the boolean result of a relational operation. 

 It would be much better to use understandable standard VHDL if address = "00" then read_mux_out <= data_out; else read_mux_out <= (others => '0'); endif; respectively an conditional assignment in concurrent code.

[Altera_Forum]

--- Quote Start ---  Thanks Mixa :)  --- Quote End ---    No problem :) just a click on "Add to cms's Reputation" link at the top rigth of the post.

[Altera_Forum]

I suspect this is one reason why some people unfairly regard VHDL as "verbose" - people write bad code and then call the lanbguage verbose because they don't use the strengths of the language to write simple clear code like the right honourable cms has just demonstrated.