Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
20764 Discussions

DMA (Direct memory access)


I am studying DMA and I have questions regarding to DMA. Questions are listed below, everyone will be highly appreciated to answer them and help me to understand the working of DMA. If you find any question IP specific then kindly give its general answer.

Q1) When DMA is a flow controller, in which condition hardware handshaking interface will be used or software handshaking interface will be used for either source or destination peripherals?

Q2) Is the hardware handshaking interface also includes single and burst request signals along with request and acknowledge signals?

Q3) When source or destination peripheral is flow controller then why hardware handshaking interface is not supported?

Q4) When DMA is a flow controller (means DMA knows the block size and DMA should transfer the data using maximum possible bursts and where possible using single or early-terminated burst), then why do peripherals request for single or burst transactions?

Q5) For peripheral-to-memory, memory-to-peripheral and peripheral-to-peripheral single or multi-block transfers, if the peripheral is either source or destination then address to read from source and address to write on destination should be fixed throughout the single or multi-block transfer. Is this a correct statement?

Q6) I have confusions in DLR (DMA Line Router) that how it selects a set of service sources from a set of DMA compatible service sources? Then how the selected service sources are further used for hardware handshaking? Kindly refer me to any resource from which I can understand the working of DLR. And also refer some resources for priority Mux for handling hardware requests from DLR.

0 Kudos
1 Reply

Hi Amir,

Any update from your side? Below are reference regarding the DMA Controller Core that could be helpful. -315



0 Kudos