I have done a Hyper RAM controller by systemverilog and communicate to it due to "mm_pipeline_bridge" in QSYS. I can write and read data into my external Hyper RAM under NIOS program. Everything work correctly while accessing as data due to BASE_ADDRESS generated by QSYS. But now I want to put my code into external Hyper RAM and gotten failure. In Linker I composed a memory device an regions with appropriate addresses (QSYS), after that I have chosen in linker ( .bss, .heap, .stack, .rodata, .rwdata, .text) tab of bsp editor and set composed regions. Everything is compiled. No errors. And all .hex files generated (on_chip_flash.hex, mm_bridge_0.hex and on_memory_0.hex). After that I have generated a .pof file and chosen option "load memory file" with "on_chip_flash.hex".
What I must do to run my code from external Hyper RAM?
Big request to all: PLEASE, DO NOT ANSWER ME IN ABSTRACT STYLE OR REFER ME TO "n2sw_nii5v2gen2.pdf" HEAD 220.127.116.11.
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A few clarification if I may, is it convenient for you to share the qsys and nios project for us to check further?
And after all the steps mention, compilation are good with no error, but after the .pof are loaded, nothing is happening without any error showing up?
Please do let me know if I misunderstand the situation.
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