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Altera_Forum
Honored Contributor I
952 Views

DMA Speed Issues

Hi all, 

 

I have a QSYS design with the basic DMA controller. I have found numerous issues with this DMA controller and have managed to work around most of the issues but stuck at one last one. 

 

Avalon to Avalon 

I can do an A2A transfer with bursting on or bursting off at 220MB/sec doing WORD transfers. With bursting I can do a max of 1024 word transaction. So everything looks good with the A2A transaction. 

 

Avalon to Physical memory issues. 

A2P doing WORD transfers there is a significant difference bursting and non-bursting mode. When bursting is on I can get 220MB/sec. I notice the address does not keep on increasing and it has to go thru the address translation table only once. However with bursting off the address keeps on increasing and it goes thru the address translation table every change in address which reduces the transfer rate to around 50MB/sec. If you look at the Signal Tap with burst off we can see the address changes every 4-6 clock ticks hence the reduced data rate, where as with bursting the address changes every clock tick. 

 

However with bursting ON, reading and writing to a constant address does not work i.e. RCON and WCON settings on the DMA core does not work and the address still keep on incrementing. This means with bursting on I cannot read and write to a FIFO. 

 

How can I prevent the address increment when I want to read from a FIFO and still achieve good speed. I intend to transfer upto 2KBytes of data at a fast rate. 

 

FYI for those who intend to use this DMA core, one major issue is that you cannot have all the options Byte, HalfWord, Word, DW, QW checked. Only check the one you intended to use others wise the system hangs. I have managed to get only Word and DW working. The QW does not work.
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5 Replies
Altera_Forum
Honored Contributor I
64 Views

The forum shrank your SignalTap captures. Not sure of the workaround, in the worst case put them in a .zip and upload again?

Altera_Forum
Honored Contributor I
64 Views

Attached are the SignalTap screen shots in the zip file. DMA burst is good speed but I cannot read from a constant address like a FIFO. Does someone have an insight into whats happening.

Altera_Forum
Honored Contributor I
64 Views

Your SignalTap didn't include the waitrequest, but I think the only thing you're seeing here is the universal truth that an external memory like SDRAM/DDR has a big performance hit when you read/write to it word-at-a-time. You need to burst to get anything reasonable performance-wise. 

 

What you need is a non-bursting read from the FIFO constant address, and a bursting write to the SDRAM/DDR memory. I think you should be able to do this with the mSGDMA. 

 

If the FIFO is embedded in an IP core of your creation, you could of course just modify your Avalon-MM to receive the burst read. Or using off-the-shelf blocks, you could also use mSGDMA Avalon-ST to Avalon-MM conversion.
Altera_Forum
Honored Contributor I
64 Views

Thanks Ted for your suggestion. I will try them out. How can I modify the Avalon slave to handle a burst read? Should I just trap the incrementing read address and output data from the FIFO which means my slave should have a larger address range? 

 

Anish 

 

 

 

--- Quote Start ---  

Your SignalTap didn't include the waitrequest, but I think the only thing you're seeing here is the universal truth that an external memory like SDRAM/DDR has a big performance hit when you read/write to it word-at-a-time. You need to burst to get anything reasonable performance-wise. 

 

What you need is a non-bursting read from the FIFO constant address, and a bursting write to the SDRAM/DDR memory. I think you should be able to do this with the mSGDMA. 

 

If the FIFO is embedded in an IP core of your creation, you could of course just modify your Avalon-MM to receive the burst read. Or using off-the-shelf blocks, you could also use mSGDMA Avalon-ST to Avalon-MM conversion. 

--- Quote End ---  

Altera_Forum
Honored Contributor I
64 Views

 

--- Quote Start ---  

Thanks Ted for your suggestion. I will try them out. How can I modify the Avalon slave to handle a burst read? Should I just trap the incrementing read address and output data from the FIFO which means my slave should have a larger address range? 

 

Anish 

--- Quote End ---  

 

 

Yes, instead of having the FIFO appear as a single address location, have it appear as a range of addresses equal to your maximum supported burst, where 'read' from any location in that range just gets the next FIFO read.
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