DMA freezing ?

[Jerome]

Hi guys,

I'm trying to make a simple design on my Intel Dev Kit MAX10 with the NIOS 2, DDR3 sdram controller and the DMA.

I write directly a pattern into my memory (1Gb in 64Mb*16) via NIOS 2 and DDR3 sdram controller, then I read back if it's well written (which is the case). And finally try to move one halfword (16bits) to another location an read again but I can't read...

I think everything is well setup in my Platform designer but then when I use the DMA to transfert data (I use registers, not HAL-drivers), I can't read back the memory...

Here is my config for the DMA :

while(IORD_ALTERA_AVALON_DMA_STATUS(DMA_BASE) == 0x02); //If DMA transaction is in progress then wait   IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0); IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0x0);   IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_BASE,0x0); //specifies the first location to be read in a DMA transaction   IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_BASE,0x2); //specifies the first location to be written in a DMA transaction   IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_BASE,2); //specifies length (in Bytes) of transfert   IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x038A); //WCON, RCON, LEEN, GO, HW to 1   while(IORD_ALTERA_AVALON_DMA_STATUS(DMA_BASE) == 0x02);   IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0x0); IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0);

Thanks for your help !

PS : if you have any example of how to use the DMA (with registers, I've also tried with HAL-drivers but I wasn't able to make it work ^^') It will be really appreciated... I looked into UG embedded IP and NIOS 2 software developer's handbook but there's no example with registers...

[NurAida_A_Intel]

Hi Sir,

You can refer to Chapter 3 (page 37) on this "UniPHY Design Tutorials" for Qsys (http://www.altera.com/literature/hb/external-memory/emi_tut_qdr.pdf). They have used DMA in the system.  The design example targets the Stratix IV FPGA development kit which includes a 16-bit wide, 1-Gb Micron MT41J64M16LA-15E 667-MHz DDR3 SDRAM component but it is helpful to get an idea on how everything should works.

Hope this is helpful for you.

Thanks

Regards,

NAli1

[Jerome]

Hi NALi1,

Thank you for your answer, that will be helpful I hope. I'm looking at the PDF. I'll be back soon if that's work ! :)

Best regards,

Jerome.

[Jerome · Accepted solution]

So,

I've found my trouble...

while(IORD_ALTERA_AVALON_DMA_STATUS(DMA_BASE) == 0x02); //If DMA transaction is in progress then wait IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0); IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0x0); IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_BASE,0x0); //specifies the first location to be read in a DMA transaction IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_BASE,0x2); //specifies the first location to be written in a DMA transaction IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_BASE,2); //specifies length (in Bytes) of transfert IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x038A); //WCON, RCON, LEEN, GO, HW to 1 while(IORD_ALTERA_AVALON_DMA_STATUS(DMA_BASE) == 0x02); IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0x0); IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0);

and then, was just pre-configuring control register before transaction...

while(IORD_ALTERA_AVALON_DMA_STATUS(DMA_BASE) == 0x02); //If DMA transaction is in progress then wait IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0382); IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0x0); IOWR_ALTERA_AVALON_DMA_RADDRESS(DMA_BASE,0x0); //specifies the first location to be read in a DMA transaction IOWR_ALTERA_AVALON_DMA_WADDRESS(DMA_BASE,0x2); //specifies the first location to be written in a DMA transaction IOWR_ALTERA_AVALON_DMA_LENGTH(DMA_BASE,2); //specifies length (in Bytes) of transfert IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x038A); //WCON, RCON, LEEN, GO, HW to 1 while(IORD_ALTERA_AVALON_DMA_STATUS(DMA_BASE) == 0x02); IOWR_ALTERA_AVALON_DMA_STATUS(DMA_BASE, 0x0); IOWR_ALTERA_AVALON_DMA_CONTROL(DMA_BASE, 0x0);