Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

DSP builder signaltap with derived_clock acquisition

Altera_Forum
Honored Contributor II
‎11-03-2014 05:22 AM
1,026 Views

Sir, 

I have trouble in signaltap data acquisition using derived clock. Problem here is 10Hz to be displayed in signaltap with 8k sample depth, but using base clock of 50Mhz seems to be impossible. I feel the derived_clock is the only option but derived_clock assigning to signal tap keeps hanging while acquiring signaltap. How do I assign derived_clock to signaltap? Pin assignment is not clear to me and Derived_clock as trigger for segmented. Please help...  

 

Thanks
0 Kudos

Link Copied

0 Replies
Reply

Community support is provided Monday to Friday. Other contact methods are available here.

Intel does not verify all solutions, including but not limited to any file transfers that may appear in this community. Accordingly, Intel disclaims all express and implied warranties, including without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement, as well as any warranty arising from course of performance, course of dealing, or usage in trade.

For more complete information about compiler optimizations, see our Optimization Notice.