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Daisy Chain JTAG & Serial configuration device connections in Cyclone - II FPGA

Altera_Forum
Honored Contributor II
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Hi, 

 

 

I am using 5 no's of FPGA Cyclone - II and i want to connect 5 FPGA's in JTAG connectivity with daisy chain configurations. As well as i want to connect individual Serial configuration devices to each FPGA with 10 pin Header to program via Altera Byte Blaster. Please find the attachments for my application. 

 

 

Finally i want to load *.bit file directly to each FPGA or program each Serial configuration devices individually. 

 

 

Please confirm whether my application can be work or not. 

 

I have referred following manuals: 

 

 

 

AN656: Page 6 of 6 in combining jtag programming of configuration device and fpga with as configuration of fpga using a configuration device and download cable 

 

Page 413 of 470 in cyclone ii device handbook, volume 1 

 

 

 

Please give your feed back as much as possible. 

 

 

Regards, 

Magalingam
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Altera_Forum
Honored Contributor II
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Hi Magalingam, 

 

Since your JTAG chain includes lots of devices, its important to include buffers/drivers on the signals. I'd recommend a buffer at the JTAG header with ESD protection, and then buffer/fanout of the TCK/TMS signals. Take a look at this example (which has 7 devices in the JTAG chain); 

 

http://www.ovro.caltech.edu/~dwh/carma_board/ 

 

http://www.ovro.caltech.edu/~dwh/carma_board/gda06rb004_carma_v0.87_dec03.pdf 

 

p7 of the schematic has a block diagram showing you the JTAG chain, p44, p77, p78 has the of the buffering. Note how the nCEO of each of the FPGAs turns off a red LED, i.e., the red LEDs are on when the FPGAs are powered by not configured. The LEDs go off once the FPGAs are configured. This makes it easy to see when the FPGAs are configured. 

 

Do these FPGAs all operate independently? If not, why not just configure them from a common source, eg., a MAX II CPLD plus a flash device containing the configuration image for all 5 FPGAs? 

 

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf 

 

You do not really need the AS headers for the SPI EEPROMs. You can use .jic programming via JTAG. 

 

Cheers, 

Dave
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chunhao
Beginner
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Hi,

I also have problem about daisy chain configurations. Can you provide the example again.

The linked page has expired...

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