Hello All,I followed an ethernet tutorial, but there it uses on-chip memory with 2 SGDMA. In this, I think I can send data from Nios to ethernet and ethernet to Nios. But I would like to send the data from FPGA. After reading, I came to know that it can be done if I push the data from FPGA to DDR3 and access DDR3 from NIOS to ethernet and vice versa. But it just theoretical. I would like to know how can I do it in ALtera tools and is this a right direction to do so? Thanking you
Hi Shameem,To design the desired system, you should use the Qsys tool to add the components and make necessary connections between them. 1. Select Tools > Qsys to open the Qsys tool, and then save the file as nios_system.qsys 2. Double-click on the clock source clk_0 and change the Clock frequency to 100000000 Hz (100MHz). Then, right-click on clk_0 and rename it as sys_clk. 3. Add a Nios II processor. The Nios II processor is used to run application programs that handle the data sent to or received from the Triple-Speed Ethernet MegaCore. 4. Add an on-chip memory, which will be used as the main memory to store programs and data for the processor. Any data received from the Triple-Speed Ethernet MegaCore will be stored in this memory as well. 5. Add a JTAG UART component. With the JTAG UART component, the Nios II processor is able to send data to the host computer, such as information that needs to be printed out to the terminal in the application program. 6. Add a Triple-Speed Ethernet MegaCore. It works as a Media Access Controller, which along with the Nios II processor and the external PHY chip are the key components of the Triple-Speed Ethernet system. For detailed information about this MegaCore, refer to the Triple-Speed Ethernet MegaCore Function User Guide. 7. Add an SGDMA controller for receive operation. This controller will be set to transfer data from a streaming interface to a memory-mapped interface, so that data can be transferred from the Triple-Speed Ethernet MegaCore to the on-chip memory. The controller will interrupt the processor whenever it finishes the data transfer. 8. Add another SGDMA controller for transmit operation. This controller governs the reading of data from the on-chip memory main_memory and sending it to the Triple-Speed Ethernet MegaCore. 9. Add another on-chip memory. Unlike the main_memory part, this on-chip memory is used to store only the descriptors of the SGDMA controllers. 10. Now, all the components have been added, but the system is not complete as there are several error messages displayed. 11. After you have resolved all error messages, you can generate the system. • Select the Generation tab. • Uncheck the Create block symbol file (bsf) in the Synthesis section as shown in Figure 10. • Click Generate on the bottom of the window. • When successfully completed, the generation process produces the message “Generate Completed”. 12.using eclipse tool generate BSP and develop software. For detailed information on above steps follow: ftp://ftp.altera.com/up/pub/altera_material/12.0/tutorials/de2-115/using_triple_speed_ethernet.pdf For Design examples://www.altera.com/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-... use niosii-ethernet-standard-4sgx230.zip file from above link and modify as per your requirements. Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
Hello Shameem,there are several ways to do a fpga to ethernet data transfer, but you must consider your needs, first of all the required speed. If the data rate is low, you can still use your current Nios hardware design to read data from a specific location in fpga (registers or shared onchip memory) and then transfer to or from ethernet. This solution is quite simple even for a beginner, provided you don't look for performance. Instead, if you have huge data and/or high data rate, probably Nios would not be able to keep up the pace and you'd need to redesign the system with a different approach. This would involve building a direct channel from fpga data source to ethernet (i.e. dma). In this case you must also consider what kind of protocol you are using on ethernet. Depending on your specifications you eventually decide if you want to design everything in hardware (maximum performance but greatest design effort) or if you still want to rely on Nios processor (simpler but limited speed).
Thank you very much for the reply.I have followed this tutorial. I think via this I can send information on ethernet from nios to PC and PC to nios. I want to use ethernet to send data from FPGA to PC and PC to FPGA via NIOS. Is this possible? Maybe I need to use DDR3 as shared memory between NIOS and FPGA. How can I do that? Thanking you
--- Quote Start --- I want to use ethernet to send data from FPGA to PC and PC to FPGA via NIOS. --- Quote End --- Where exactly does the data come from? Since it's already on fpga it should be straightforward for Nios to read it and sent it to ethernet. As I said before, I guess the data is stored into registers or onchip ram; in this case you only need share it or provide dual port access and connect to Nios data bus. If your data comes from any other source, like a serial port or PIO, you only need to add the proper interface component in Qsys and, again, connect to Nios on the other side.
Thank you for your reply.It is data acquisition system from a camera. The Camera gets 15 frames per second with 600 * 800 pixels. Each pixel is 8 bit and I want to transfer this pixel to the PC via ethernet. will this system will work for this system? Do I have made them in the form of frames or it will handle via NIOS? It will be helpful if there are any example projects available. Thank you in advance.
From your figures I see that you must transfer 7.2MBytes/s, if you use raw uncompressed data. I think your actual Nios system could hardly manage it; please note that Nios is a rather slow processor.What you can do is implement a sgdma channel to move data from camera front end to the ethernet and use Nios to start/stop/supervise the transfer. Moreover you must use a fast ethernet protocol because the tcp/ip you are probably using in your current design can not sustain such a high data rate (I guess you are using SSS sample or something similar). IIRC there is at least one reference design in the altera wiki or in the knowledge base on altera website.