Error in Modulesim verilog

[Altera_Forum]

my program is compile successfully without saving but when i save the project transcript shows error unexpected integers error  

 module auto_segment (output [6:0]hex 0,input clk); integer count; always@(posedge clk); begin if(count<9) count<=count+1; else count<=0; end endmodule

[Altera_Forum]

HI, 

 Try changing your code from integer count; to reg [3:0] count;  Thanks.  Regards, spdl2001 (This message was posted on behalf of Intel Corporation)

[Altera_Forum]

Why not post the actual error?

[Altera_Forum]

always@(posedge clk); 

 Notice the semi-colon after the always? It shouldn't be there - you basically ended the always block after that line.  Always indent your code properly, and always use begin and end statements after each "always", "if", "else", "for", and "initial" block. Even if that statement is just one line. It makes it far easier to see what is going on.  I also always put the begin on the same line as the "always"/"if"/"else"/etc. statement because it's easier to avoid making mistakes like semi-colons where they shouldn't be.

[Altera_Forum]

You also don't have either an initial value (integer count = 0;), or a reset signal, meaning modelsim will never output anything other than 'xxxxx' for count because there is never any time that it gets set to a known value, not depending on its current value.

[Altera_Forum]

Hi Adnan Riar, 

 Error in line 4. remove semicolon from always statement. Please find the correct code.  module auto_segment(output hex,input clk); integer count; always@(posedge clk) begin if(count<9)begin count<=count + 1; end else begin count<=0; end end endmodule   Best Regards, Tzi Khang, Lim (This message was posted on behalf of Intel Corporation)