Altera AFE told me that for the DQ,DM,DQS VREF is generated internally since it is POD12 standard. For command/address/control signals VREF is not needed because all this signals are output. The only signal that might need VREF is ALERT_N, but Quartus sets its standard to 1.2V not SSTL-12 so it does not use VREF. Also in the pin-out file that Quartus generates for DDR4 design all fileds for VREF pins are emtpy, whereas for DDR3 design it shows 0.75V.
Your FAE is correct, my bad. I've been using the Arria 10 SoC dev kit with the DDR4 HiLo interface for well over a year now. The HiLo interface is designed to support different memory standards, so on the dev kit the VREF pins in the memory banks are set to HILO_VDDQ/2. I was fooled by that and forgot about POD12 for DDR4 using internal VREF. Documentation for this is vague and hard to find, which I'm sure is why you posted here. This is all I have been able to find about it (from the Arria 10 Core Fabric and General Purpose I/Os Handbook):126.96.36.199 Guideline: VREF Sources and VREF Pins For Arria 10 devices, consider the following VREF pins guidelines: • Arria 10 devices support internal and external VREF sources. You can use the internal VREF with calibration to support DDR4 using the POD12 I/O standard. — There is an external VREF pin for every I/O bank, providing one external VREF source for all I/Os in the same bank. — Each I/O lane in the bank also has its own internal VREF generator. You can configure each I/O lane independently to use its internal VREF or the I/O bank's external VREF source. All I/O pins in the same I/O lane will use the same VREF source. Not exactly clear-cut.