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Altera_Forum
Honored Contributor I
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De0 Nano SoC Ethernet

Hello, I have a DE0 Nano SoC board (Cyclone V 5CSEMA4U23C6), and I am interested in learning about the Ethernet on it (Micrel KSZ9031RN PHY Chip). And I was wondering if the FPGA can directly interact with this (I assume it can). 

 

I was also wondering if there is any documentation on using it, and some examples... 

 

Thanks!
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Altera_Forum
Honored Contributor I
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--- Quote Start ---  

Hello, I have a DE0 Nano SoC board (Cyclone V 5CSEMA4U23C6), and I am interested in learning about the Ethernet on it (Micrel KSZ9031RN PHY Chip). And I was wondering if the FPGA can directly interact with this (I assume it can). 

 

I was also wondering if there is any documentation on using it, and some examples... 

 

Thanks! 

--- Quote End ---  

 

 

Dated topic but similar question was raised somewhere so I'll reply here. The DE0-Nano-SoC board has Ethernet PHY connected to the HPS I/O. Thus, it make sense to use the HPS (instead of the FPGA) to utilize the Ethernet. 

 

The interesting part is if you really want to use the FPGA soft IP MAC (instead of the hard MAC in the HPS) and connect it to the Ethernet PHY, it *could (take with huge grain of salt) be possible by assigning these HPS I/O pins as the Loan I/O and exposing them to the FPGA fabric. However, there is no example today that uses the FPGA TSE MAC + KSZ9031RN PHY --> you'll have to port things like MDIO, PHY delay settings, etc  

 

Long story short, stick with HPS MAC if you are just planning to transfer data from one system to another, and move any relevant data via the H2F bridge to the FPGA core :)
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