De0-cv jtag

[Altera_Forum]

Hi all, 

 I'm working on an academic project which will involve pulling information over a JTAG interface. I am considering the DE0-CV board but I can't find much information about how its JTAG works or if it even supports it. I've looked through the Cyclone V handbook and on page 254 it does not seem to be listed however the board appears to at least have the JTAG pins. Would anyone be able to clarify? Thanks!

[Altera_Forum]

Yes - the DE0-CV uses JTAG for programming the Cyclone V FPGA. However, the FPGA's JTAG is terminated on-board, to Altera's USB-Blaster circuit. There is no direct access to the FPGA's JTAG signals.  

 The only JTAG signals that are exposed (via J5) are those for the CPLD. However, this device is part of the USB-Blaster circuit. I strongly recommend you leave these be - you'll easily render the board unusable should you do the wrong thing with this device. These JTAG signals do not offer access to the FPGA.  The USB port on the DE0-CV offers you access to the FPGA, via the Blaster circuit & JTAG, and can be used with Altera's software and programming scripts. I'd suggest that can help you with a "project which will involve pulling information over a jtag interface".  Cheers, Alex