Programmable Devices
CPLDs, FPGAs, SoC FPGAs, Configuration, and Transceivers
Announcements
FPGA community forums and blogs on community.intel.com are migrating to the new Altera Community and are read-only. For urgent support needs during this transition, please visit the FPGA Design Resources page or contact an Altera Authorized Distributor.
21615 Discussions

Dedicated Clock (CLK) pins

CLa_R
Novice
1,767 Views

In my Altera Cyclone IV EP4CE10 Pin Information document, I see pins CLK1...7.

 

Can I use this pins as normal IO (mono or bidirezional) pins?

 

 

0 Kudos
3 Replies
AnandRaj_S_Intel
Employee
857 Views

Hi,

 

Yes _CLKOUTp or _CLKOUTn pins can be used as IO(mono or bidirectional) or clock.

https://www.thailand.intel.com/content/dam/www/programmable/us/en/pdfs/literature/dp/cyclone-iv/pcg-01008.pdf

 

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

 

Best Regards,

Anand Raj Shankar

(This message was posted on behalf of Intel Corporation)

 

0 Kudos
CLa_R
Novice
857 Views

Thanks for your ansewer.

If I read well, in the document you showed me, the pins labeled DIFFCLK [1..7], as in my case, can be used ONLY as input pins

0 Kudos
AnandRaj_S_Intel
Employee
857 Views

Hi,

 

Yes, ​DIFFCLK  or CLK are dedicated clock pin can be used only as Input pin.

We can also cross check using quartus tool too, we expect fitter error for such a scenario.

 

Best Regards,

Anand Raj Shankar

0 Kudos
Reply