I'm seeing an issue with enabling a LVDS on an Arria 10 (10AS066N3F40E2SG Arria 10 Soc Dev Kit) when trying to place an LVDS transmitter.
I have created an Altera LVDS Serdes using IP Parameter Editor. I have set the LVDS to the following settings:
# Channels: 1
Data Rate: 890.1 Mbps
Serdes Factor: 8
I'm letting the LVDS supply the PLL, using a refclk of 100MHz and creating two additional clocks for some complementary logic (148.5MHz and 38.4MHz).
I can place this down at the IP top level (top level verilog wrapper) and I assign it to pins F9/G9 (FMC A LA17_CC_P/N connection).
The main design is based on the Arria10 GHRD, with this LVDS added at the top level.
During the fitter, I continue to get the following errors:
Error (14566): The Fitter cannot place 1 periphery component(s) due to conflicts with existing constraints (1 LVDS_CLOCK_TREE(s)). Fix the errors described in the submessages, and then rerun the Fitter. The Intel FPGA Knowledge Database may also contain articles with information on how to resolve this periphery placement failure. Review the errors and then visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number. Error (175001): The Fitter cannot place 1 LVDS_CLOCK_TREE, which is within Altera LVDS SERDES dsi_tx_serdes_single_altera_lvds_171_tqdaopa. Info (14596): Information about the failing component(s): Info (175028): The LVDS_CLOCK_TREE name(s): dsi_tx_serdes_single:u_dsi_tx_serdes_single_CLK|dsi_tx_serdes_single_altera_lvds_171_tqdaopa:lvds_0|dsi_tx_serdes_single_altera_lvds_core20_171_fux255i:core|altera_lvds_core20:arch_inst|default_lvds_clock_tree.lvds_clock_tree_inst Error (16234): No legal location could be found out of 32 considered location(s). Reasons why each location could not be used are summarized below: Error (175008): Location was not in the legal region (30 locations affected) Info (175029): LVDSCLOCKTREE_X78_Y32_N4 Info (175029): LVDSCLOCKTREE_X78_Y32_N5 Info (175029): LVDSCLOCKTREE_X78_Y60_N4 Info (175029): LVDSCLOCKTREE_X78_Y60_N5 Info (175029): LVDSCLOCKTREE_X78_Y87_N4 Info (175029): LVDSCLOCKTREE_X78_Y87_N5 Info (175029): LVDSCLOCKTREE_X78_Y114_N4 Info (175029): LVDSCLOCKTREE_X78_Y114_N5 Info (175029): LVDSCLOCKTREE_X78_Y141_N4 Info (175029): LVDSCLOCKTREE_X78_Y141_N5 Info (175029): LVDSCLOCKTREE_X78_Y168_N4 Info (175029): LVDSCLOCKTREE_X78_Y168_N5 Info (175029): and 18 more locations not displayed Error (175006): Could not find path between the LVDS_CLOCK_TREE and destination LVDS_CHANNEL Info (175027): Destination: LVDS_CHANNEL dsi_tx_serdes_single:u_dsi_tx_serdes_single_CLK|dsi_tx_serdes_single_altera_lvds_171_tqdaopa:lvds_0|dsi_tx_serdes_single_altera_lvds_core20_171_fux255i:core|altera_lvds_core20:arch_inst|channels.tx.serdes_dpa_inst~CHANNEL Info (175015): The I/O pad dsi_clk is constrained to the location PIN_F9 due to: User Location Constraints (PIN_F9) Info (14709): The constrained I/O pad is contained within a pin, which is contained within this LVDS_CHANNEL Error (175022): The LVDS_CLOCK_TREE could not be placed in any location to satisfy its connectivity requirements Info (175021): The LVDS_CHANNEL was placed in location LVDS_CHANNEL containing F9 Info (175029): 2 locations affected Info (175029): LVDSCLOCKTREE_X78_Y5_N4 Info (175029): LVDSCLOCKTREE_X78_Y5_N5
I've looked through several of the LVDS documents, but I'm not entirely sure why this is happening, and honestly, I'm confused as to how to even debug why it's doing this. I've tried several different scenarios, using the main 100MHz refclk that is the driving the main GHRD logic, and added support CLK_50MHZ_FPGA that comes in on AN18. Neither seemed to make a difference.
Ideally I want to make a 5 channel LVDS, but wanted to start with one to ensure my setup was correct.
Any help would be greatly appreciated. Thanks!
Thanks for the feedback! So I let Quartus perform auto-assign. The LVDS pin assignment where I was getting errors assigning it to F9/G9, wants to auto assign to AW16. I believe that it tried to place it here, since (as a test) I connected the LVDS internal PLL to an external clock that is on AP18 (which is in the same BANK 2A.
So I'm using a FMC daughtercard which, for this particular design, requires me to connect shared LVDS pairs to the 3G and 3F IO Banks.
So my questions are:
Feel free to point me to any docs that can clear this up. I had read through a few, but could not find the answer to what I was looking for (or wasn't sure exactly what to search for)