Dedicated clock pin feeding lvds_rx ip ?

[Altera_Forum]

Hi, 

 Is it possible to use a clock dedicated input pin in lvds standard to feed a lvds_rx rx_in pin ? I have this error in quartus (11.0 sp1): Error: Can't place pin "clkoutP" with an I/O register at location J27 that does not support I/O registers  Is there any solution to use this pin ?  Thanks.

[Altera_Forum]

Which FPGA family? What are you exactly connecting to the pin, a LVDS receive MegaFunction?

[Altera_Forum]

Hi, 

It's a cyclone III (EP3C80F780). I have several lvds pairs but only one pair is connected to a dedicated clock input pin. I need to connect all these pins to a altlvds_rx megafunction but I have an error for the clock input.

[Altera_Forum]

This sounds like a Quartus bug, because Cyclone III hasn't input registers at all. As the device manual clarifies, DDR input registers (the building block for the LVDS_RX MegaFunction) are implemented in LE registers. 

 P.S.: I reviewed the implementation of LVDS_RX in Cyclone III resource property editor and it looks like if it is using input registers. Then it's clear why the clock inputs can't be regularly used as LVDS RX input.

[Altera_Forum]

What's your LVDS data rate? If it's not near Cyclone III limits, an implementation in LE registers should work.

[Altera_Forum]

Hi, 

 Thanks for your answer and sorry for replying late.  I feed the altlvds_rx with a 310MHz clock / deserialization factor x10. Even with a desialization factor of x2 I still have an error: "... location xx does not support I/O registers".  Is there any way to force the compability of this dedicated clock pin with the IO registers function which is required by allvds_rx ?

[Altera_Forum]

Do you think it's possible to by-pass this error? 

 Thanks,  Sébastien.