Delay chain design?

[Altera_Forum]

Hi 

 I am using the cycloneIII 3c120 kit to learn designing with FPGA.  What I would like to do is a delay chain, in which a signal is delayed by each chain element on the order of 100..500ps. Since such small times can not be designed by clocked flip flops (?), I would like to use LEs, which produce delay just from entry to output. The amount of delay elements would be of the order of 20 to 100, since I would like to cover about 10 ns. Higher delays can be done synchronously.   I think that such a delayline is not very precise, since the delay of each element might vary over time, temperature etc., but at least it could be causal in the sense that an earlier element should bring a smaller delay.  Up to now, I have not been capable of making such a delay line. The elements exhibit very strange delays, even later elements bring smaller delays etc.  I think, that this is a typical beginners question, any help is much appreciated  best regards  Flexi

[Altera_Forum]

If you need delay lines, you design is probably flawed. 

Why do you want one?

[Altera_Forum]

The delay line is there to support very small times, which can not be reached by synchronous design AFAIK. So, by delaying an edge through a delay line, I can get finer information.

[Altera_Forum]

So I had a project where we actually had a need to do this. Nowdays the IO actually has dynamically programmable delay elements. 

 However, you essentially need to connect a bunch of ALUTs in cascade. Then you need a mux or muxes (more ALUTs) to dynamically select which "tap" you want. You can also allow dynamically bypass ALUTs in the cascade. In order for this to work you have to control the placement of each ALUT so as to keep your design reproducable.  Then the final step ... characterize. You'll have to try the various permutations of your selections to see what delays you get.  In our case exact delay was not required as we merely need statistical coverage of delays.

[Altera_Forum]

--- Quote Start ---  The delay line is there to support very small times, which can not be reached by synchronous design AFAIK. So, by delaying an edge through a delay line, I can get finer information.  --- Quote End ---    what kind of information. You still havent said what the purpose is.

[Altera_Forum]

The delay line is there to fill the gap: when I want to measure a signal, let's say a 1pps-signal, but not with a clock of 100 MHz, but 1GHz or higher, I can delay the 1pps signal and find out when the clock fits the delay. Is it now clear?

[Altera_Forum]

FPGA internal fabric is not designed to run with signals that run at GHz speed. Delays using ALUTs are normally only to scew a signal at an output or input put, not internally. If the input signal is running at GHz speeds, you will need to use one of the high speed GX transeivers (available on GX FPGAs), and maybe an associated IP core. 

 I dont think you'll be able to do what you want using the normal internals of an FPGA.

[Altera_Forum]

The signals that I process are not at GHz, but the times measured should be below 1 ns. The signals are quite slow (1 pulse per second) 

 I think, that the FPGA could be used to make a delay, as I could do this using hardware inverters. Why does this not work?

[Altera_Forum]

I dont quite understand what you're measuring. Is it the length of the pulse?

[Altera_Forum]

yes, I want to measure the length of the 1pps signal, but more precise than with 100MHz.

[Altera_Forum]

There are various previous threads related to implementing logic cell delays.  

 http://www.alteraforum.com/forum/showthread.php?t=27284 http://www.alteraforum.com/forum/showthread.php?t=19328  Apart from general PVT (process, voltage, temperature) variations affecting the accuracy of logic cell delays, there are some specific problems that make it unlikely to get uniform delay steps in the design. It's mainly due to the core and routing resources structure and the way, how they are handled by the place and route tool.

[Altera_Forum]

Just a thought. If you use Serdes you may be able to do what you want. you will need to pass say 0101 pattern regularly at high speed then switch to your pulse (ORed) and convert to parallel word e.g. 32 bits then you will read the word to indicate length of your pulse, possibly a pattern like this may be read...01010111111110101...

[Altera_Forum]

Hi FvM, hi kaz 

 Thank you for your information. Can one make restrictions for placing designs into specific LEs? I assume, that this would help make a more predictable behavior. As stated, I would like to measure a pulse of 1 second to a precision of about 100..500ps, which can not be done with sync design on 3c120. The idea of using delays comes from a seminar on femtosecond counters, which I found on the internet. FPGA should be ok because of the lot of cells they have... But I am a beginner...

[Altera_Forum]

Hi, 

 What you have read is true about asynchronous design methodology which is not the practice in FPGAs. FPGAs are designed for synchronous RTL approach. The FPGA logic fabric is too slow for femtosec counting.  FPGA fabric registers cannot run in speeds beyond say 400MHz, in fact I once tried wiring (just wiring) 800MHz signal through and it was corrupted.  So no matter what restrictions you make on LEs, it is not going to help. At the end you need a time reference to suit your requirement in gigahertz.  You may consider using the serdes (in effect a fast asic part of FPGA) but for 1 sec pulse you need plenty of work before fpga. For example you can toggle your pule into 0101 pattern while sending another regular idle pattern then you can let serdes detect the start and end of 0101.. but I guess this is too harsh to be practical.

[Altera_Forum]

If you review the Altera Froum threads related to TDC designs, you'll find reports about implementations utilizing the carry chain, which is in fact the fastest available resource for asynchronous delays. There's also a previous discussion about using Gigabit transceivers for timing measurements. 

 Constraining LE locations won't be sufficient, you would also need to take command over the route selections, which isn't provided by the tool as far as I see. It would also require to understand exactly the available connections for individual LUT inputs, which is more complex than in may appear at first sight, at least for Cyclone III devices. The inputs have different delays and connection capabilities as the resource property editor reveals - and are freely changed during design routing.  A basically simple method for picosecond range timing measurements is using analog time-to-voltage conversion (and succeding digitizing).

[Altera_Forum]

--- Quote Start ---  yes, I want to measure the length of the 1pps signal, but more precise than with 100MHz.  --- Quote End ---    Maybe, you can use a TDC to measure it outside FPGA.

[Altera_Forum]

Hi, Flexi. 

 Curious if and how you solved your 100-500ps resolution issue. I've done something similar in the past in a Cyclone III, IIRC, and I'm toying with it again in a Stratix IV, which is what prompted the search. I'm seeing what amounts to ~46pS per tap on average through the delay line. It's not 100% monotonic, but fairly linear, with some outliers. If you need 500ps resolution, you can probably do some post processing of the taps to get what you need.  It is, of course, very sensitive to process, voltage, and temperature. If you look at the paths with Timequest, the same paths at the fast and slow corners are about 2:1. So if you're going to use something like this, you'd best have some means of real-time, dynamic calibration.  In any case, I was wondering what you came up with, and I'd be happy to compare notes with you.  Thanks, Matt

[Altera_Forum]

hi guys! 

sorry i don't know how to post a new thread but i hope you cn help me from here. i have a schematic design on quartus that i need to add a delay.can you help me designing the delay? also please can you show me how to post a thead of my own Thank